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引用次数: 12
摘要
本文提出了一种基于n点ntt核的可参数化n系数多项式乘法器的设计，该乘法器采用收缩阵列。设计的基于ntt的多项式乘法器用通用结构VHDL语言描述;用Quartus II V. 13在Stratix EP4SGX230KF40C2上合成;使用Modelsim验证;并在95.64 μs内求出两个4095次多项式的乘积。硬件综合和性能结果表明，所设计的多项式乘法器具有良好的面积-时间权衡性能，适合于基于格的密码系统的硬件实现。
Hardware design of an NTT-based polynomial multiplier
This paper presents the design of a parameterizable n-coefficient polynomial multiplier based on an n-point NTT-core, which uses a systolic array. The designed NTT-based polynomial multiplier is described in generic structural VHDL; synthesized on the Stratix EP4SGX230KF40C2 using Quartus II V. 13; verified using Modelsim; and performs the product of two polynomials of degree 4095 in 95.64 μs. The hardware synthesis and performance results show that the designed polynomial multiplier presents a good area-time trade-off and it is suitable for hardware implementations of lattice-based cryptosystems.
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