Hardware design of an NTT-based polynomial multiplier

Abstract

This paper presents the design of a parameterizable n-coefficient polynomial multiplier based on an n-point NTT-core, which uses a systolic array. The designed NTT-based polynomial multiplier is described in generic structural VHDL; synthesized on the Stratix EP4SGX230KF40C2 using Quartus II V. 13; verified using Modelsim; and performs the product of two polynomials of degree 4095 in 95.64 μs. The hardware synthesis and performance results show that the designed polynomial multiplier presents a good area-time trade-off and it is suitable for hardware implementations of lattice-based cryptosystems.