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2014 IX Southern Conference on Programmable Logic (SPL)最新文献

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Burst-mode asynchronous controller implementation on FPG using relative timing 利用相对定时技术在FPG上实现突发模式异步控制器
2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002213
Jotham Vaddaboina Manoranjan, K. Stevens
{"title":"Burst-mode asynchronous controller implementation on FPG using relative timing","authors":"Jotham Vaddaboina Manoranjan, K. Stevens","doi":"10.1109/SPL.2014.7002213","DOIUrl":"https://doi.org/10.1109/SPL.2014.7002213","url":null,"abstract":"A new methodology for the design of glitch free burst-mode asynchronous controllers on FPGAs is presented. The approach is based on relative timing, which enables timing driven asynchronous design. On ASICs, relative timing based asynchronous designs have achieved notable benefits in terms of power, performance and area, when compared to their synchronous counterparts. This paper adopts the relative timing based design methodology on FPGAs and presents a methodology to extract and map timing constraints to guarantee correct operation. The method presented in this paper can be used to implement a wide variety of burst-mode controllers, across various FPGAs. This will form the foundation for seamless ASIC prototyping of asynchronous designs on FPGAs as well as implementation of low power asynchronous designs on FPGAs.","PeriodicalId":320882,"journal":{"name":"2014 IX Southern Conference on Programmable Logic (SPL)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128486700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Design and implementation of decimal fixed-point square root in LUT-6 FPGAs LUT-6 fpga中小数点平方根的设计与实现
2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002211
M. Vazquez, M. Tosini
{"title":"Design and implementation of decimal fixed-point square root in LUT-6 FPGAs","authors":"M. Vazquez, M. Tosini","doi":"10.1109/SPL.2014.7002211","DOIUrl":"https://doi.org/10.1109/SPL.2014.7002211","url":null,"abstract":"This paper presents the design and implementation of a digit-recurrence algorithm for determining the decimal square root in a 6-input LUT-based FPGA device. The design is based on the efficient use of resources such as the carry-chain originally devoted to the binary addition. Clock frequencies of 98.5 MHz (71 ns latency), 93.4 Mhz (173 ns latency) and 84.7 MHz (402 ns latency) were obtained for operand widths of 7, 16 and 34 digits, respectively, in a Xilinx Virtex 6 FPGA.","PeriodicalId":320882,"journal":{"name":"2014 IX Southern Conference on Programmable Logic (SPL)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130265079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An advanced NoC with debug services on FPGA FPGA上具有调试服务的高级NoC
2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002201
E. Todorovich, M. Leonetti, R. Brinks
{"title":"An advanced NoC with debug services on FPGA","authors":"E. Todorovich, M. Leonetti, R. Brinks","doi":"10.1109/SPL.2014.7002201","DOIUrl":"https://doi.org/10.1109/SPL.2014.7002201","url":null,"abstract":"A modern system-on-a-chip includes tens to hundreds of modules such as processor cores, memories and other IP blocks and exchanges packetized data using high-performance interconnection networks as a subsystem for data transport. This paper reports the implementation of an industry-wide network on a chip in FPGA, and the first implementation and evaluation of the Sonics Performance Monitor and Hardware Tracer integrated in NoC IP cores, with area, time, and power measurements on a current FPGA device.","PeriodicalId":320882,"journal":{"name":"2014 IX Southern Conference on Programmable Logic (SPL)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116998516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Automated multi-vendor platform for FPGA design 自动化多厂商FPGA设计平台
2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002219
Jose Mosquera, Guillermo H. Reggiani, R. Cayssials, E. Ferro
{"title":"Automated multi-vendor platform for FPGA design","authors":"Jose Mosquera, Guillermo H. Reggiani, R. Cayssials, E. Ferro","doi":"10.1109/SPL.2014.7002219","DOIUrl":"https://doi.org/10.1109/SPL.2014.7002219","url":null,"abstract":"Nowadays, Field Programmable Gate Arrays (FPGAs) are used in very diverse applications. Modern FPGA devices offer high capacity to implement digital design with a wide range of specific resources. Typically, FPGA vendors categorize theirs devices in families suitable for: (1) high performance applications or (2) low-cost designs. On the other hand, FPGA manufacturers offer different design tools with diverse configuration options to get the most of the available FPGA resources for each design implemented. Usually, designers adopt for new projects the same criteria, devices and tools used in previous projects since it is time consuming to evaluate alternatives from others FPGA manufacturers. In this paper, we present an automated design platform used to evaluate different alternatives to implement FPGA designs. Evaluation involved technical as well as economic criteria that may help the designer to find the most adequate alternative to its design.","PeriodicalId":320882,"journal":{"name":"2014 IX Southern Conference on Programmable Logic (SPL)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121563460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Arbitrary waveform generator using FPGA for applications in ultrafast scan voltammetry 任意波形发生器利用FPGA在超快扫描伏安法中的应用
2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002220
C. Maffrand, Didimo Zarate, M. Zón, Héctor Fernández, M. R. Romero
{"title":"Arbitrary waveform generator using FPGA for applications in ultrafast scan voltammetry","authors":"C. Maffrand, Didimo Zarate, M. Zón, Héctor Fernández, M. R. Romero","doi":"10.1109/SPL.2014.7002220","DOIUrl":"https://doi.org/10.1109/SPL.2014.7002220","url":null,"abstract":"This paper presents an arbitrary waveform generator (AWG) based on field-programmable-gate-array (FPGA) technology and a 12 bit digital-to-analog converter (DAC). It has a user interface with a PS/2 keyboard and a 16×2 character LCD display. The system is mounted on a printed circuit board which includes the DAC and analog amplification stages. This device has been developed as part of a system for laboratory experiments for ultrafast scan voltammetry (UFSV).","PeriodicalId":320882,"journal":{"name":"2014 IX Southern Conference on Programmable Logic (SPL)","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131440001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
PUF's performance evaluation among different Xilinx FPGAs families PUF在不同赛灵思fpga系列中的性能评估
2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002210
Brisbane Ovilla-Martínez, A. Díaz-Pérez
{"title":"PUF's performance evaluation among different Xilinx FPGAs families","authors":"Brisbane Ovilla-Martínez, A. Díaz-Pérez","doi":"10.1109/SPL.2014.7002210","DOIUrl":"https://doi.org/10.1109/SPL.2014.7002210","url":null,"abstract":"The FPGAs have been used as a platform to implement and validate the Physical Unclonable Function con-structions. The authors validate PUFs performance using several know metrics (reliability, uniqueness, uniformity, and bit aliasing) and these test are conducted just on the FPGA used to the implementation. The problem arises when we want to use a PUF tested on a specific FPGA family into another, there is no assurance that the behavior of a PUF is the same among different families of FPGA. Up to our knowledge no previous work has been reported to evaluate PUF designs for different FPGA families and manufacturing technology. Additional, in this paper we proposed three PUF schemes based in the combination of two previous PUFs designs: BUT and LUT. All schemes were implemented and evaluated with main PUF metrics, on Spartan-3E, Spartan-6, and Virtex-5. An analysis of the results allows us to determine which FPGA platform have good behavior and what is the performance impact by the environmental variations.","PeriodicalId":320882,"journal":{"name":"2014 IX Southern Conference on Programmable Logic (SPL)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134019314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FPGA structures with concentrated vs distributed memory for images comparison 具有集中与分布式存储器的FPGA结构用于图像比较
2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002207
S. Geninatti, G. Gennai, Santiago Roatta, E. Boemo
{"title":"FPGA structures with concentrated vs distributed memory for images comparison","authors":"S. Geninatti, G. Gennai, Santiago Roatta, E. Boemo","doi":"10.1109/SPL.2014.7002207","DOIUrl":"https://doi.org/10.1109/SPL.2014.7002207","url":null,"abstract":"This paper proposes a strategy for calculating the windowed correlation between histograms using FPGA. The processing is done extracting image features directly from the compressed video stream. Thus, maximum speed is obtained; the circuit can manage up to 200.000 photograms per second. Two options for calculating the histogr am are proposed: one based on distributed registers, and other based on blocks of RAM. The performance of the two a Iternatives is compared. Exhaustive registers-level segmentation for the algorithms and block memory-level segmentation for histograms is applied. The final circuit is evaluated taking into account its adaptation to different video resolutions, number of histogram bins, parallelism in the concurrent computation, and progress of FPGA technology.","PeriodicalId":320882,"journal":{"name":"2014 IX Southern Conference on Programmable Logic (SPL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131296914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power estimations vs. power measurements in Spartan-6 devices Spartan-6设备中的功率估计与功率测量
2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002214
J. Oliver, Julio Perez Acle, E. Boemo
{"title":"Power estimations vs. power measurements in Spartan-6 devices","authors":"J. Oliver, Julio Perez Acle, E. Boemo","doi":"10.1109/SPL.2014.7002214","DOIUrl":"https://doi.org/10.1109/SPL.2014.7002214","url":null,"abstract":"Experimental measurements of power consumption for core logic of a 45-nm Spartan-6 FPGA and the comparison with the values predicted by the power estimation tool are presented. The measurement setup, benchmark suite, and EDA flows utilized to obtain power estimations are described. Several types of multipliers implemented in both LUTs and embedded blocks have been utilized as case-studies. They include versions with different levels of pipelining. In addition, a set of actual circuits obtained from OpenCores is analyzed. Main results of power estimations errors are presented and compared.","PeriodicalId":320882,"journal":{"name":"2014 IX Southern Conference on Programmable Logic (SPL)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131418972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
FPGA implementation of a binary32 floating point cube root FPGA实现的一个binary32浮点立方根
2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002202
Carlos Eduardo Minchola Guardia, E. Boemo
{"title":"FPGA implementation of a binary32 floating point cube root","authors":"Carlos Eduardo Minchola Guardia, E. Boemo","doi":"10.1109/SPL.2014.7002202","DOIUrl":"https://doi.org/10.1109/SPL.2014.7002202","url":null,"abstract":"This paper presents the implementation of a sequential hardware core to compute a single floating point cube root compliant with the current IEEE 754-2008 standard. The design is based on Newton-Raphson recurrence, reciprocal and cube root units are implemented. Optimal performance requires two iterations for reciprocal and one for cube root units obtaining an accurate approximation of +/- 3 least significant bits. Our proposal is able to be performed up to 149 Mhz over Virtex5. The hardware cost occupies 230 Slices and 12 Dsp48s taking a latency of 19 clock cycles.","PeriodicalId":320882,"journal":{"name":"2014 IX Southern Conference on Programmable Logic (SPL)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123475716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Ro-based PRNG: FPGA implementation and stochastic analysis 基于ro的PRNG: FPGA实现与随机分析
2014 IX Southern Conference on Programmable Logic (SPL) Pub Date : 2014-11-01 DOI: 10.1109/SPL.2014.7002221
L. De Micco, M. Antonelli, H. Larrondo, E. Boemo
{"title":"Ro-based PRNG: FPGA implementation and stochastic analysis","authors":"L. De Micco, M. Antonelli, H. Larrondo, E. Boemo","doi":"10.1109/SPL.2014.7002221","DOIUrl":"https://doi.org/10.1109/SPL.2014.7002221","url":null,"abstract":"This paper deals with the use of Ring Oscillators (ROs) as pseudo random number generators (PRNG). The design, made for ALTERA Cyclone III ©, using low level primitives is explained. Two relevant characteristics of a PRNG are considered to validate the design: 1) the equiprobability of all possible outcomes and 2) the statistical independence of consecutive values. In this work these properties are measured via Information Theory Quantifiers. A dual entropy plane is used to represent the time series and easily visualize the results obtained with different configurations. The quality is also compared with other available PRNGs by means of the dual entropy plane. Our method constitutes an effective reduction of the complete analysis made with test suites like DIEHARD or NIST.","PeriodicalId":320882,"journal":{"name":"2014 IX Southern Conference on Programmable Logic (SPL)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128165747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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