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2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.最新文献

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Copper via chain under etching process improvement 铜经链下蚀刻工艺改进
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493206
J. Ji, M. Zhang, W. Dong, A. Guo, S. Liang, S. Liao, C. Niou, K. Chien
{"title":"Copper via chain under etching process improvement","authors":"J. Ji, M. Zhang, W. Dong, A. Guo, S. Liang, S. Liao, C. Niou, K. Chien","doi":"10.1109/RELPHY.2005.1493206","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493206","url":null,"abstract":"Via under etching is one of the Cu dual damascene process related concerns. This paper presents our findings of localized via chain under etching and the proces improvement on the WAT (wafer accept test) test structure. We used a variety of failure analysis tools and techniques to provide timely results on via chain open failures. The employed fault isolation methods include PVC (passive voltage contrast) and OBIRCH (optical beam induced resistance change). The physical analysis methods include FIB (focused ion beam) and TEM (transmission electron microscope). A new model and method were developed for solving localized via under etching.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"59 15","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131638401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Failure analysis of intermittent pin-to-pin short caused by phosphorous particle in molding compound 模塑料中磷颗粒引起的断续引脚短路失效分析
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493152
N. Wang, Jin Wu, S. Daniel
{"title":"Failure analysis of intermittent pin-to-pin short caused by phosphorous particle in molding compound","authors":"N. Wang, Jin Wu, S. Daniel","doi":"10.1109/RELPHY.2005.1493152","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493152","url":null,"abstract":"Many \"intermittent pin-to-pin short\" cases have occurred in LSI packages that are processed with a molding compound containing phosphorus as a flame-retardant. The failure always occurred after a few months to one year of usage, but all stress methods that have been tried seem unable to accelerate the failure before field usage. The paper describes an experimental investigation into ways of detecting phosphorous particles. Two kinds of phosphorous particles were seen in the device. A broken coating one formed an acid solution pool and caused a spider shaped growth of copper particles. It also formed a shorting path that resulted in the intermittent pin-to-pin short. The large copper particle that coexisted with phosphorous particles is the body of the spider. Soft X-ray can reveal large and medium particles near the failed pin. Focused ion beam (FIB) using passive voltage contrast (PVC) can reveal the spider shape that forms shorting path. EDS mapping provides not only the shorting path but also materials information.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126689330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Impact of proton irradiation on the RF performance of 0.12 /spl mu/m CMOS technology [MOSFET devices] 质子辐照对0.12 /spl μ l /m CMOS技术[MOSFET器件]射频性能的影响
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493112
S. Venkataraman, B. Haugerud, E. Zhao, B. Banerjee, A. Sutton, P. Marshall, Chang-Ho Lee, J. Cressler, J. Laskar, J. Papapolymerou, A. Joseph
{"title":"Impact of proton irradiation on the RF performance of 0.12 /spl mu/m CMOS technology [MOSFET devices]","authors":"S. Venkataraman, B. Haugerud, E. Zhao, B. Banerjee, A. Sutton, P. Marshall, Chang-Ho Lee, J. Cressler, J. Laskar, J. Papapolymerou, A. Joseph","doi":"10.1109/RELPHY.2005.1493112","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493112","url":null,"abstract":"The effects of 63 MeV proton irradiation on the DC and RF performance of a 0.12 /spl mu/m CMOS technology is presented for the first time. The radiation response of the CMOS devices was investigated up to an equivalent total gamma dose of 1.0 Mrad(Si). Measurements of the DC current-voltage, low-frequency (1/f) noise, S-parameters, and broadband noise characteristics of the devices were performed before and after irradiation at room temperature. These scaled CMOS devices show a very slight degradation of threshold voltage, transconductance (g/sub m/), and 1/f noise after proton irradiation without any intentional radiation hardening. High-frequency measurements on the irradiated devices show that there is very little or no perceptible degradation of S-parameters, cut-off frequency (f/sub T/), or broadband noise characteristics to 1 Mrad(Si) exposure levels. These results suggest that this 0.12 /spl mu/m CMOS technology is well-suited for the development of total-dose radiation tolerant analog and RF circuits without additional radiation hardening.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"25 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133086474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Short and long-term safe operating area considerations in LDMOS transistors LDMOS晶体管的短期和长期安全工作区域考虑
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493145
P. Hower, S. Pendharkar
{"title":"Short and long-term safe operating area considerations in LDMOS transistors","authors":"P. Hower, S. Pendharkar","doi":"10.1109/RELPHY.2005.1493145","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493145","url":null,"abstract":"Lateral DMOS transistors are widely used in mixed-signal IC circuit designs, particularly where power handling is important. This paper views the LDMOS from a power-handling perspective, considering both design and characterization aspects. The complex nature of the LDMOS safe operating area (SOA) can be dealt with by considering long-term and short-term operating conditions. Long-term conditions are covered by a hot carrier SOA, and short-term conditions are further sub-divided into electrical SOA and thermal SOA. Characterization examples of the various kinds of SOA are given.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"226 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113980726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
Radiation-induced clock jitter and race 辐射引起的时钟抖动和赛跑
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493087
N. Seifert, P. Shipley, M. Pant, V. Ambrose, B. Gill
{"title":"Radiation-induced clock jitter and race","authors":"N. Seifert, P. Shipley, M. Pant, V. Ambrose, B. Gill","doi":"10.1109/RELPHY.2005.1493087","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493087","url":null,"abstract":"The paper assesses the reliability risk due to radiation-induced single event upsets (SEU) of clock nodes for flip flop and pulse latch based designs. Two basic upset modes are identified: radiation-induced clock jitter and radiation-induced race. Our simulation results indicate that the radiation-induced clock soft error rate (SER) cannot be neglected on the chip-level. Particularly for pulse latch based designs, upsets occurring in the clock generator have the potential to dominate the chip-level SER if no mitigation techniques are applied. Our results show that the hardened pulse latch in combination with a hardened and shared pulse generator yields a 20/spl times/ improvement in sequential SER as well as the lowest susceptibility to radiation-induced race and clock jitter with little area and performance penalty.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124366669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 88
Structural and thermal investigation for FBAR reliability in wireless applications 无线应用中FBAR可靠性的结构和热研究
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493109
R. Fillit, B. Ivira, J. Boussey, R. Fortunier, P. Ancey
{"title":"Structural and thermal investigation for FBAR reliability in wireless applications","authors":"R. Fillit, B. Ivira, J. Boussey, R. Fortunier, P. Ancey","doi":"10.1109/RELPHY.2005.1493109","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493109","url":null,"abstract":"This paper describes work carried out to assess the failure mechanisms of film bulk acoustic resonators (FBARs) developed for wireless applications. Two experimental benches were setup: one X-ray based (including diffraction, radiography and fluorescence analysis) and, for the first time, a high resolution infrared, in-situ thermal mapping apparatus. Finite element modeling was used to draw out the self heating of those components under high RF signal levels. In the paper, we describe each of those setups and highlight the improvements provided by their use when evaluating FBAR failure analysis mechanisms.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116794269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Process-induced trapping of charge in PECVD dielectrics for RF MEMS capacitive switches 射频MEMS电容开关用PECVD介质中过程诱导的电荷捕获
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493107
J. R. Webster, C. Dyck, C. Nordquist, J. Felix, M. Shaneyfelt, J. Schwank, J. Banks
{"title":"Process-induced trapping of charge in PECVD dielectrics for RF MEMS capacitive switches","authors":"J. R. Webster, C. Dyck, C. Nordquist, J. Felix, M. Shaneyfelt, J. Schwank, J. Banks","doi":"10.1109/RELPHY.2005.1493107","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493107","url":null,"abstract":"Charge-induced failure is recognized as the primary reliability issue in RF MEMS capacitive switches. In this paper, we present a simplified method for quantifying the effects of process-induced charging of PECVD dielectrics commonly used in the fabrication of these devices. Using this method, based on capacitance-voltage (C-V) measurements of MIS (metal-insulator-semiconductor) devices, we examined the charge behavior of PECVD silicon dioxide, nitride, and oxynitride films deposited at substrate temperatures of 250-350/spl deg/C. The results show that these PECVD dielectrics contain sufficient incorporated charge in their as-deposited state to inhibit reliable switch operation. Post-deposition, plasma-induced and electrical stresses were also found to negatively impact the charge behavior of these films. However, after an initial period of instability, chemical analysis showed film composition to be highly consistent, both across deposition runs and with post-deposition stress. We conclude by presenting potential techniques for mitigation of the incorporated charge observed in these PECVD dielectrics.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129767065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Investigation into the correlation of wafer sort and reliability yield using electrical stress testing 用电应力试验研究晶圆分类与可靠性良率的相关性
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493199
A. Flynn, S. Millar
{"title":"Investigation into the correlation of wafer sort and reliability yield using electrical stress testing","authors":"A. Flynn, S. Millar","doi":"10.1109/RELPHY.2005.1493199","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493199","url":null,"abstract":"We present our findings of implementing an electrical stress test on a mature CMOS product and its implications from a reliability point of view. We show that such a test, when carefully optimised, can act as an effective replacement for standard production burn-in. We also demonstrate a method for eliminating \"weak\" die at wafer sort (and hence lowered test costs) based on the measurement of standby current at specific stages of the test program.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128659845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The energy driven paradigm of NMOSFET hot carrier effects NMOSFET热载子效应的能量驱动模式
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493216
S. Rauch, G. La Rosa
{"title":"The energy driven paradigm of NMOSFET hot carrier effects","authors":"S. Rauch, G. La Rosa","doi":"10.1109/RELPHY.2005.1493216","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493216","url":null,"abstract":"As NMOSFET size and voltage are scaled down, the electron energy distribution becomes increasingly dependent only on the applied bias, because of quasi-ballistic transport over the high field region. A new paradigm of NMOSFET hot carrier behavior is proposed here, in which the fundamental driving force is available energy, rather than peak lateral electric field as it is in the lucky electron model (LEM.) This approach allows an experimental determination of S/sub IT/ (the interface state generation cross section) as a function of electron energy.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129088489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
The influence of a silicon dioxide-filled trench isolation structure and implanted sub-collector on latchup robustness 填充二氧化硅沟槽隔离结构和植入副集电极对闭锁稳健性的影响
2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. Pub Date : 2005-04-17 DOI: 10.1109/RELPHY.2005.1493072
S. Voldman, E. Gebreselasie, L. Lanzerotti, T. Larsen, N. Feilchenfeld, S. St. Onge, A. Joseph, J. Dunn
{"title":"The influence of a silicon dioxide-filled trench isolation structure and implanted sub-collector on latchup robustness","authors":"S. Voldman, E. Gebreselasie, L. Lanzerotti, T. Larsen, N. Feilchenfeld, S. St. Onge, A. Joseph, J. Dunn","doi":"10.1109/RELPHY.2005.1493072","DOIUrl":"https://doi.org/10.1109/RELPHY.2005.1493072","url":null,"abstract":"This paper demonstrates the effect of a new low-cost oxide filled trench isolation structure, and implanted sub-collectors, on the latchup robustness. With scaling and focus on low-cost wireless technology, new technologies are being developed utilizing a shallower oxide-filled trench structure and low-doped implanted sub-collectors. In this paper, the first latchup measurements and corresponding new discoveries are shown, utilizing this new isolation structure and its integration with implanted sub-collectors. This paper compares latchup measurements with the base CMOS technology (e.g. standard dual well p-substrate base technology) to quantify the net improvement. The results are shown with trench isolation only, sub-collector only, and the combined effect of the trench isolation and sub-collector.","PeriodicalId":320150,"journal":{"name":"2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual.","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125517380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
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