Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing最新文献_第2页

Modeling test cost of ownership 建模测试的所有权成本

Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing Pub Date : 1994-05-16 DOI: 10.1109/ICEDTM.1994.496087

D. Dance

引用次数: 3

Design evaluation of pipelined processors using finite state machine analysis with Markov chains 基于马尔可夫链的有限状态机分析的流水线处理器设计评价

Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing Pub Date : 1994-05-16 DOI: 10.1109/ICEDTM.1994.496103

I. H. Unwala, H. Cragon

{"title":"Design evaluation of pipelined processors using finite state machine analysis with Markov chains","authors":"I. H. Unwala, H. Cragon","doi":"10.1109/ICEDTM.1994.496103","DOIUrl":"https://doi.org/10.1109/ICEDTM.1994.496103","url":null,"abstract":"Performance evaluation of processor pipelines is required to\u0000scrutinize new and existing designs. General techniques of performance\u0000evaluation, simulation and analytical, have their strengths and\u0000weaknesses. Simulation is recommended for accurate results during final\u0000testing, while analytical is recommended for fast response time in early\u0000testing. This paper presents an analytical technique for determining\u0000processor pipeline performance that can reduce time and cost in the\u0000early design cycle when rapid response to “what if?”\u0000questions is most beneficial to the designer. The analytic model starts\u0000with a processor pipeline modeled as a finite state machine (FSM) that\u0000can be mapped on to a discrete-time Markov chain. The pipeline state\u0000model is described in detail. Large instruction traces are analyzed to\u0000extract the state transition probabilities for the Markov chain.\u0000Utilizing the properties of the Markov chain, the steady state\u0000probabilities can then be determined. The steady state probabilities are\u0000use to determine such measures as clocks per instruction, stage\u0000utilization, blocking and efficiency of the pipeline. Delays due to\u0000cache misses, true dependencies and branching can also be incorporated\u0000in the solution. An implementation of the Markov chain based dynamic\u0000instruction trace analyzer for MIPS R2000/R3000 is described and its\u0000results are presented","PeriodicalId":319739,"journal":{"name":"Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114938177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Synthesizing testable systolic arrays 合成可测试的收缩阵列

Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing Pub Date : 1994-05-16 DOI: 10.1109/ICEDTM.1994.496093

M. Evans, W. Marnane

引用次数: 0

ULSI design-for-manufacturability: a yield enhancement approach ULSI可制造性设计:一种良率提高方法

Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing Pub Date : 1994-05-16 DOI: 10.1109/ICEDTM.1994.496095

A. Tyagi, M. Bayoumi

引用次数: 3

Test strategy selection for multi-chip systems 多芯片系统的测试策略选择

Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing Pub Date : 1994-05-16 DOI: 10.1109/ICEDTM.1994.496097

M. Fares, B. Kaminska

引用次数: 1

Simultaneous partitioning, scheduling and allocation for synthesis of multi-chip module architectures 综合多芯片模块体系结构的同步分区、调度和分配

Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing Pub Date : 1994-05-16 DOI: 10.1109/ICEDTM.1994.496100

R. V. Cherabuddi, L. Chiou, M. Bayoumi

引用次数: 3

Some trends in CAD, test and fabrication of circuits and systems 电路和系统的CAD、测试和制造的发展趋势

Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing Pub Date : 1994-05-16 DOI: 10.1109/ICEDTM.1994.496085

B. Courtois

引用次数: 0

Economic analysis of test and known good die for multichip assemblies 对多芯片组件的测试和已知好的模具进行经济分析

Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing Pub Date : 1994-05-16 DOI: 10.1109/ICEDTM.1994.496098

C. Murphy, M. Abadir, P. Sandborn

{"title":"Economic analysis of test and known good die for multichip assemblies","authors":"C. Murphy, M. Abadir, P. Sandborn","doi":"10.1109/ICEDTM.1994.496098","DOIUrl":"https://doi.org/10.1109/ICEDTM.1994.496098","url":null,"abstract":"The cost and quality of a multichip assembly is highly dependent\u0000upon the cost and quality of the incoming die. In the case of a bare die\u0000assembly, it is often highly desirable to use either Known Good Die\u0000(KGD) or die that have been burned-in and tested to the same level of\u0000quality and reliability as their packaged die equivalents. However,\u0000performing full bare die burn-in and test may not always be cost\u0000effective. This paper examines the question of whether it is always\u0000necessary to use KGD to produce a cost-effective multichip module (MCM)\u0000of acceptable quality. A process-flow based cost model is used to\u0000compare the cost and quality of MCMs assembled with KGD to MCMs\u0000assembled with die that have received wafer-level test only. In addition\u0000to test effectiveness at the wafer, die, and module level, factors that\u0000are considered include die complexity (size and I/O), number of die per\u0000MCM, the cost of producing the KGD, and rework costs and effectiveness.\u0000The cost model captures inputs from wafer fabrication through MCM\u0000assembly and rework. Monte Carlo simulation is used to account for\u0000uncertainty in the input data. The resulting sensitivity analyses give\u0000final MCM cost and quality as a function of the various factors for both\u0000KGD and die that have received wafer-level test only","PeriodicalId":319739,"journal":{"name":"Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125573165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Function multiplexing minimizes pin count requirements 功能复用最小化引脚计数要求

Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing Pub Date : 1900-01-01 DOI: 10.1109/ICEDTM.1994.496092

O. Yishay

{"title":"Function multiplexing minimizes pin count requirements","authors":"O. Yishay","doi":"10.1109/ICEDTM.1994.496092","DOIUrl":"https://doi.org/10.1109/ICEDTM.1994.496092","url":null,"abstract":"The Motorola Modular Family (MMF) is currently composed of two\u0000major groups of products; the MC68HC16 family, based on the CPU16 core,\u0000and the MC68HC300 family, based on the CPU32 core. Each product in the\u0000MMF contains a CPU module, a system integration module, which controls\u0000internal to external bus cycles, and one or more of the other modules\u0000available in this family. A new system integration module has been\u0000designed to utilize reduced pin count packages for decreased cost. A\u0000multiplexed test mode allows microcontroller's internal signals to be\u0000driven or to be tested even when the pin, previously used to carry the\u0000data, is not implemented. This test mode allows the minimum pin set to\u0000provide the same controllability and observability as was present during\u0000the original test pattern development, and thus provides the same fault\u0000coverage. The internal bus protocol must be met, and internal timing\u0000must be identical to the one used before. The cost to develop the high\u0000fault grade test patterns was very high, and the time to write the\u0000patterns was very long-up to several years","PeriodicalId":319739,"journal":{"name":"Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115964784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Economic Resource Sharing in ATM Network ATM网络中的经济资源共享

Proceedings of 3rd International Workshop on the Economics of Design, Test and Manufacturing Pub Date : 1900-01-01 DOI: 10.1109/ICEDTM.1994.496105

Jiann-Liang Chen, GinKou Ma, Bau-Shuh, P. Lin

引用次数: 0