Synthesizing testable systolic arrays

Abstract

The testability of a design can be assessed subjectively using estimates and a scoring system. Objective assessment requires a Test Vector Generation (TVG) effort as well as Design for Test (DFT) hardware changes. However assessing the testability of different systolic arrays which implement the same algorithm can contain a large TVG cost. We develop an integrated design and test methodology for systolic arrays, which generates a set of test vectors early in the design cycle, thus eliminating the TVG cost from the design evaluation. Hence testability can be considered alongside traditional design considerations such as performance