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2006 IEEE Workshop on Signal Processing Systems Design and Implementation最新文献

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An Examination of the Effect of Feature Size Scaling on Effective Power Consumption in Analog to Digital Converters 特征尺寸缩放对模数转换器有效功耗影响的研究
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352580
K. Boyle, S. Kilambi, R. Dlugosz, K. Iniewski, V. Gaudet
{"title":"An Examination of the Effect of Feature Size Scaling on Effective Power Consumption in Analog to Digital Converters","authors":"K. Boyle, S. Kilambi, R. Dlugosz, K. Iniewski, V. Gaudet","doi":"10.1109/SIPS.2006.352580","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352580","url":null,"abstract":"Wireless sensor network (WSN) nodes require components with ultra-low power consumption, as they must operate without an external power supply. One technique for reducing consumption of a system is to scale it to a smaller technology; however, in recent technologies is not clear whether the decrease in dynamic power consumption outweighs the increase in static power consumption (due to leakage currents). Here this is considered by examining the power consumption of three implementations of an analog to digital converter (ADC). One in 350 nm, one in 180 nm, and one in 90 nm, were simulated and compared. The results show that the dynamic power consumption was reduced by a factor of four over the three technologies, but standby power consumption increased by an order of magnitude. The power consumption of the 180 nm implementation was always lower than the 350 nm implementation. However, assuming a WSN application with a duty cycle of 1%, the effective power consumption of the 90 nm ADC was higher than both the 180 nm and the 350 nm implementation. This highlights the dominance of leakage current in determining the effective power consumption in low-throughput nodes","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"261 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122690402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the Convergence of the Frequency-Domain LMS Adaptive Filter using LMS-DFT 基于LMS- dft的频域LMS自适应滤波器的收敛性
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352601
T. Ogunfunmi, Thomas K. Paul
{"title":"On the Convergence of the Frequency-Domain LMS Adaptive Filter using LMS-DFT","authors":"T. Ogunfunmi, Thomas K. Paul","doi":"10.1109/SIPS.2006.352601","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352601","url":null,"abstract":"This paper presents an analysis of the convergence of the frequency-domain LMS adaptive filter when the DFT is computed using the LMS steepest descent algorithm. In this case, the frequency-domain adaptive filter is implemented with a cascade of two sections, each updated using the LMS algorithm. Since the structure contains two adaptive algorithms updating in parallel, an analysis of the overall system convergence needs to consider the effect of the two adaptive algorithms on each other, in addition to their individual convergence. Analysis was done based on the expected mean-square coefficient error for each of the two LMS adaptive algorithms, with some simplifying approximations for the second algorithm, to describe the convergence behavior of the overall system. Simulations were used to verify the results","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128907648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An Energy-Efficient Reconfigurable Baseband Processor for Flexible Radios 一种用于柔性无线电的节能可重构基带处理器
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352615
A. Poon
{"title":"An Energy-Efficient Reconfigurable Baseband Processor for Flexible Radios","authors":"A. Poon","doi":"10.1109/SIPS.2006.352615","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352615","url":null,"abstract":"Most existing techniques for reconfigurable processors focus on the computation model. This paper focuses on increasing the granularity of configurable units without compromising flexibility. This is carried out by matching the granularity to the degree-of-freedom (DOF) processing in most wireless systems. A design flow that accelerates the exploration of tradeoffs among various micro-architecture for the configurable unit is discussed. A prototype processor is implemented using the Intel 0.13 mum CMOS low-power standard cell library. The estimated energy efficiency is on the same order of dedicated hardware implementations","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130691062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Low-Power Folded Programmable FIR Architecture 一种低功耗折叠可编程FIR结构
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352579
Li-Hsun Chen, O. Chen
{"title":"A Low-Power Folded Programmable FIR Architecture","authors":"Li-Hsun Chen, O. Chen","doi":"10.1109/SIPS.2006.352579","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352579","url":null,"abstract":"Based on the radix-4 Booth algorithm, a scheme that integrates tap folding and coefficient folding is proposed to design a programmable finite impulse response (FIR) architecture with low power dissipation. In addition, without increasing hardware complexity and degrading computational performance, the effective selection on input data is realized to lower the operating frequencies of the latches and multiplexers involved with the input data. With the reduction on the frequency of the input data being selected to the Booth decoders, the power consumed in the Booth decoders can be also minimized. The proposed and conventional FIR architectures are implemented using the TSMC 0.18 mum CMOS technology. The areas and power consumption of these architectures are analyzed and compared. Under the same specifications and throughput rate, the results revealed that in comparison to the conventional architectures, the proposed FIR architecture not only saves about 18.18% to 39.19% of area occupied, it also reduces 14.23% to 25.56% in power consumption","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"1 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130918327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Instruction Transfer And Storage Exploration for Low Energy VLIWs 低能量VLIWs的指令传输与存储探索
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352597
T. Aa, M. Jayapala, H. Corporaal, F. Catthoor, Geert Deconinck
{"title":"Instruction Transfer And Storage Exploration for Low Energy VLIWs","authors":"T. Aa, M. Jayapala, H. Corporaal, F. Catthoor, Geert Deconinck","doi":"10.1109/SIPS.2006.352597","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352597","url":null,"abstract":"For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled clustered loop buffers are potentially very energy efficient. However current compilers for VLIW do not fully exploit the potentials offered by such a clustered organization. This paper presents ITSE, Instruction Transfer and Storage Exploration, a methodology to minimize the instruction memory energy using a software controlled clustered loop buffer as a basis. Results for the MediaBench application suite show 61% reduction (on average) in energy in the instruction memory hierarchy as compared to traditional, existing non-clustered approaches to the loop buffer without compromising performance","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126220119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An Iterative Method for Frame-Level Adaptive Wiener Interpolation Filters in Video Coding 视频编码中帧级自适应维纳插值滤波的迭代方法
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352565
Jianpeng Dong, N. Ling
{"title":"An Iterative Method for Frame-Level Adaptive Wiener Interpolation Filters in Video Coding","authors":"Jianpeng Dong, N. Ling","doi":"10.1109/SIPS.2006.352565","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352565","url":null,"abstract":"In this paper we present an iterative method for improving frame-level adaptive Wiener filtering in video coding. Our method iteratively computes Wiener filter coefficients using the motion field, macroblock partitioning and best coding modes, which are in turn updated in the motion estimation and compensation process using the computed filters. To control the computational complexity of the iterative method, we also propose a termination condition using the mean Euclidean distance of the filter coefficients between consecutive iterations. With extensive computer simulations, we found that our proposed iterative Wiener filtering method produces significant bit rate saving (3.4% on the average) while maintaining the same level of peak-signal-to-noise-ratio (PSNR), compared to the JM 10.1 reference software for H.264/AVC. Most of the performance gain comes from a few iterations at the very beginning. As the number of iteration increases, the further bit rate reduction is less than 1%. Therefore, to achieve the best balance between computational complexity and performance gain, we believe computing Wiener filter coefficients using just 2-3 iterations will suffice","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133077550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories 基于多单元NAND闪存的低功耗高通量BCH纠错VLSI设计
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352599
W. Liu, Junrye Rho, Wonyong Sung
{"title":"Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories","authors":"W. Liu, Junrye Rho, Wonyong Sung","doi":"10.1109/SIPS.2006.352599","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352599","url":null,"abstract":"As the reliability is a critical issue for new generation multi-level cell (MLC) flash memories, there is growing call for fast and compact error correction code (ECC) circuit with minimum impact on memory access time and chip area. This paper presents a high-throughput and low-power ECC scheme for MLC NAND flash memories. The BCH encoder and decoder architecture features byte-wise processing and a low complexity key equation solver using a simplified Berlekamp-Massey algorithm. Resource sharing and power reduction techniques are also applied. Synthesized using 0.25-mum CMOS technology in a supply voltage of 2.5 V, the proposed BCH (4148,4096) encoder/decoder achieves byte-wise processing, and it needs an estimated cell area of 0.2 mm2, and an average power of 3.18 mW with 50 MB/s throughput","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129250905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 178
Limiting Flexibility in Multiplication over GF(2m): A Design Methodology GF(2m)乘法的极限灵活性:一种设计方法
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352572
W. Chelton, M. Benaissa
{"title":"Limiting Flexibility in Multiplication over GF(2m): A Design Methodology","authors":"W. Chelton, M. Benaissa","doi":"10.1109/SIPS.2006.352572","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352572","url":null,"abstract":"Multiplication over the field GF(2m) is computationally expensive, not least because the operation involves modulo reduction. It is typical to fix the field and field representation to improve performance, but some applications need to operate over multiple fields. This work investigates the cost of this flexibility with application to elliptic curve cryptography (ECC), both analytically and empirically through FPGA implementation. A design methodology is presented for limiting the flexibility to a number of prescribed fields with the representation fixed for each, and the methodology is applied to the design of a bit-serial multiplier over GF(2m). FPGA implementation results are given; and it is shown that the practical advantage of the proposed approach is considerable in terms of speed versus area trade-off. In fact, only a 12.3% area overhead was incurred by the flexible implementation compared to the fixed field implementation, while still achieving the same speed performance","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115818925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and Implementation of JPEG 2000 Codec with Bit-Plane Scalable Architecture 基于位平面可扩展架构的jpeg2000编解码器的设计与实现
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352621
Yu-Wei Chang, Chih-Chi Cheng, Chun-Chia Chen, Hung-Chi Fang, Liang-Gee Chen
{"title":"Design and Implementation of JPEG 2000 Codec with Bit-Plane Scalable Architecture","authors":"Yu-Wei Chang, Chih-Chi Cheng, Chun-Chia Chen, Hung-Chi Fang, Liang-Gee Chen","doi":"10.1109/SIPS.2006.352621","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352621","url":null,"abstract":"In this paper, an area-efficient JPEG 2000 codec is implemented on 6.1 mm2 with 0.18 mum CMOS technology dissipating 180 mW at 1.8 V and 60 MHz. It is capable of processing 78 MS/s for lossy coding at 1 bpp and 50 MS/s for lossless coding. Four techniques are used to implement this chip. The pre-compress ion rate-distortion optimization (pre-RDO) determines truncation points before coding to reduce computations for the EBC. The dataflow conversion and embedded compression reduces the tile memory bandwidth. The bit-plane parallel context formation enables scalable bit-plane coding. Experimental results show this chip has higher area efficiency than the previous works","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125613382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Shortened Impulse Response Filter (SIRF) Scheme for Cost-Effective Echo Canceller Design of 10GBase-T Ethernet System 一种用于10GBase-T以太网系统高性价比回波消除设计的缩短脉冲响应滤波器(SIRF)方案
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352600
Ming-Feng Hsu, Yen-Liang Chen, Kai-Yuan Jheng, A. Wu
{"title":"A Shortened Impulse Response Filter (SIRF) Scheme for Cost-Effective Echo Canceller Design of 10GBase-T Ethernet System","authors":"Ming-Feng Hsu, Yen-Liang Chen, Kai-Yuan Jheng, A. Wu","doi":"10.1109/SIPS.2006.352600","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352600","url":null,"abstract":"IEEE 802.3 an task force is now developing new Ethernet standard-10GBase-T. Currently, most of the 10Gbps Ethernet is developed with fiber medium due to the fiber high bandwidth. However, the fiber and optical device cost are still too high to be popular. Therefore, our goal is to lower the 10GBase-T transceiver cost. We propose two new low cost 10GBase-T transceiver architectures. One is echo shortening. A shortened impulse response filter (SIRF) is used to shorten the echo impulse response to reduce the echo canceller cost. The other is joint shortening. The SIRF is used to jointly shorten impulse response of echo and NEXT. Moreover, compare with the conventional architecture, the cost saving of the proposed echo shortening and joint shortening architecture is 12% and 35% respectively","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131323159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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