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2006 IEEE Workshop on Signal Processing Systems Design and Implementation最新文献

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Carry Prediction and Selection for Truncated Multiplication 截断乘法的进位预测与选择
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352605
R. Michard, A. Tisserand, Nicolas Veyrat-Charvillon
{"title":"Carry Prediction and Selection for Truncated Multiplication","authors":"R. Michard, A. Tisserand, Nicolas Veyrat-Charvillon","doi":"10.1109/SIPS.2006.352605","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352605","url":null,"abstract":"This paper presents an error compensation method for truncated multiplication. From two n-bit operands, the operator produces an n-bit product with small error compared to the 2n-bit exact product. The method is based on a logical computation followed by a simplification process. The filtering parameter used in the simplification process helps to control the trade-off between hardware cost and accuracy. The proposed truncated multiplication scheme has been synthesized on an FPGA platform. It gives a better accuracy over area ratio than previous well-known schemes such as the constant correcting and variable correcting truncation schemes (CCT and VCT)","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133888619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Low-Power Saturated Arithmetic and its Application in VLSI Architectures for OFDM Modems OFDM调制解调器的低功率饱和算法及其在VLSI架构中的应用
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352581
K. Karagianni, Vassilis Paliouras, Th. Giannopoulos
{"title":"Low-Power Saturated Arithmetic and its Application in VLSI Architectures for OFDM Modems","authors":"K. Karagianni, Vassilis Paliouras, Th. Giannopoulos","doi":"10.1109/SIPS.2006.352581","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352581","url":null,"abstract":"The impact or a modified saturated arithmetic on power dissipation and signal quality produced by building blocks of a multicarrier modem is studied in this paper. The proposed simplified saturation scheme is shown to significantly reduce the switching activity of the arithmetic circuits, while it requires reduced hardware complexity for its implementation. Power estimation of synthesized circuits reveals power savings of up to 20%, depending on signal quality. The proposed saturation scheme is shown to moderately increase the power of noise, therefore leaving signal quality practically unaffected. The applicability of the proposed saturation is demonstrated by quantifying signal noise power behavior for various types of digital filters and radix-2 FFT structures suitable for OFDM modems","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115896990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
H.264 Video Decoder Design: Beyond RTL Design Implementation H.264视频解码器设计:超越RTL设计实现
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352564
Youngsoo Kim, W. Edmonson
{"title":"H.264 Video Decoder Design: Beyond RTL Design Implementation","authors":"Youngsoo Kim, W. Edmonson","doi":"10.1109/SIPS.2006.352564","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352564","url":null,"abstract":"We present two case studies of different architectures for H.264 video decoder. The objective of this case study is to show the design methodology that can maximize the flexibility of video decoder. First, H.264 is designed based on configurable processor. The configurable processor was used to complement the existing functional units with instruction extensions for the H.264 hardware kernel. Secondly, we profile the H.264 application to capture the amount of data traffic among modules. We will use this information to guide the placement of H.264 hardware modules in the dataflow architecture. A simulated annealing based placement algorithm produces the final placement aiming to optimize the communication costs between the modules in a dataflow architecture. With both our design methodologies, emerging embedded applications requiring several GOPS to meet real-time constraints can be drafted within a reasonable amount of design time with maximum design flexibility","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124829430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Analog-Counter-Based Conscience Mechanism in Kohonen's Neural Network Implemented in CMOS 0.18 μm Technology 基于CMOS 0.18 μm技术实现的Kohonen神经网络模拟-计数器良心机制
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352619
T. Talaśka, R. Wojtyna, R. Dlugosz, K. Iniewski, W. Pedrycz
{"title":"Analog-Counter-Based Conscience Mechanism in Kohonen's Neural Network Implemented in CMOS 0.18 μm Technology","authors":"T. Talaśka, R. Wojtyna, R. Dlugosz, K. Iniewski, W. Pedrycz","doi":"10.1109/SIPS.2006.352619","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352619","url":null,"abstract":"In this study, we present a hardware implementation of the conscience mechanism in Kohonen self-organizing maps. The proposed realization of the conscience mechanism is important to the functioning of the neural network as it eliminates so-called dead (inactive) neurons. As a result the network learning, the level quantization error can be reduced. The conscience mechanism and the Winner Take All (WTA) block have been implemented in 0.18 μm CMOS process. The implementation of the conscience mechanism itself occupies 1200 μm 2 and its maximum power consumption is 9.5 μW. The WTA block together with the conscience mechanism occupies 0.024 mm2 and dissipates 55 μ W","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124983856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Desing and Optimization of a Programmable Instruction Decoder for DSP Architecture 基于DSP架构的可编程指令解码器的设计与优化
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352604
Yong-Kyu Jung
{"title":"Desing and Optimization of a Programmable Instruction Decoder for DSP Architecture","authors":"Yong-Kyu Jung","doi":"10.1109/SIPS.2006.352604","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352604","url":null,"abstract":"A hardware/software co-reconfiguration technique is introduced to design a programmable instruction decoder for DSP systems that do not employ field-programmable gate-array. This technique allows software developers to swiftly and accurately retarget their DSP systems. In order to present the reconfiguration procedures and performance evaluations of the technique, a reconfigurable instruction decoder (RID) for Texas Instruments' TMS320C55 DSPs was implemented and optimized","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132744426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Digit-Serial Systolic Architectures for Inversions over GF(2m) GF(2m)上反转的数字串行收缩结构
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352559
Zhiyuan Yan
{"title":"Digit-Serial Systolic Architectures for Inversions over GF(2m)","authors":"Zhiyuan Yan","doi":"10.1109/SIPS.2006.352559","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352559","url":null,"abstract":"Digit-serial architectures for finite field arithmetic operations are of interest since hardware costs can be optimized by minimizing the digit size to satisfy throughput requirements. Based on a reformulation of the extended Euclidean algorithm, we design digit-serial systolic architectures with digit size L for inversions over GF(2m) using a systematic approach. Compared with previously proposed digit-serial inversion architectures, our new architectures require significantly less hardware and reduce critical path delays by 50% while achieving the same throughput L/m and latency. Unlike previously proposed digit-serial inversion architectures, for which L has to be a divisor of m, our systematic approach is applicable even when L is not a divisor of m","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122752300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Carry Estimation for Two's Complement Fixed-Width Multipliers 二补定宽乘法器的进位估计
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352606
Yen-Chin Liao, Hsie-Chia Chang, Chih-Wei Liu
{"title":"Carry Estimation for Two's Complement Fixed-Width Multipliers","authors":"Yen-Chin Liao, Hsie-Chia Chang, Chih-Wei Liu","doi":"10.1109/SIPS.2006.352606","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352606","url":null,"abstract":"An n-bit fixed-width multiplier keeps the input-width and output-width the same by truncating the n least significant output bits. In order to reduce the complexity, direct-truncation multipliers omit the half of the partial products corresponding to the truncated part. However, a large truncation error will be introduced. Thus, error compensation, which equals to estimating the carry bits, is required. In this paper, three carry estimation schemes based on the dependency among the partial products and the inputs are proposed. Not only this dependency is investigated, statistical analysis for these estimation approaches is provided. Applying the proposed schemes, at least 84% the truncation error can be reduced","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"299302 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116580815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
A Method for Object Tracking using Shape Matching 一种基于形状匹配的目标跟踪方法
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352611
Qi Xiaoping, Zhang Qiheng, Ouyang Yimin, Ma Jiaguang
{"title":"A Method for Object Tracking using Shape Matching","authors":"Qi Xiaoping, Zhang Qiheng, Ouyang Yimin, Ma Jiaguang","doi":"10.1109/SIPS.2006.352611","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352611","url":null,"abstract":"Using shape-initialized deformable template, a new method for object tracking is presented. This method consists of two steps: 1) searching step, by background predicting, moving object is segmented, then detecting the edge, thinning edge, and select landmark points to construct a shape model which contains all the feature points of the shape; 2) tracking step, using prior shape model which is extracted from the previous frames to implement the coarse location of object by shape matching, then adjusting shape model to obtain the inter-frame change of the object by adopting active contour model, to achieve accurate location and generate a updating shape model for object detection in next frame. The results of experiments demonstrate that the mentioned algorithm has strong adaptability to deformation, pose change, lighting change, and occlusion","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115441212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High-Speed Pipelined EGG Processor on FPGA 基于FPGA的高速流水线EGG处理器
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352569
W. Chelton, M. Benaissa
{"title":"High-Speed Pipelined EGG Processor on FPGA","authors":"W. Chelton, M. Benaissa","doi":"10.1109/SIPS.2006.352569","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352569","url":null,"abstract":"This paper details the design of a new high-speed pipelined elliptic curve cryptography (ECC) application specific instruction set processor (ASIP) using field programmable gate array (FPGA) technology. A six-stage pipeline has been applied to the design, and pipeline stalls are avoided via instruction reordering and data forwarding. Three complex instructions are introduced to reduce the latency by reducing the overall number of instructions. The new processor shows improvements over previously reported designs in terms of throughput, latency and area. The higher clock frequencies and low latencies lead to the fastest point multiplication time reported in the literature. An FPGA implementation over GF(2163) is shown, which achieves a point multiplication time of 36.77 microseconds at 77.01 MHz on a Xilinx Virtex-E device-over 50% faster than the best figure previously reported","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"168 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115172261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Low Power Trellis Decoder with Overscaled Supply Voltage 供电电压过刻度的低功率栅格解码器
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352582
Yang Liu, Tong Zhang, Jiang Hu
{"title":"Low Power Trellis Decoder with Overscaled Supply Voltage","authors":"Yang Liu, Tong Zhang, Jiang Hu","doi":"10.1109/SIPS.2006.352582","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352582","url":null,"abstract":"This paper is interested in applying voltage over-scaling (VOS) to reduce trellis decoder energy consumption, where the key issue is how to minimize the decoding performance degradation due to VOS-induced errors. Based on the fact that the integrity of different bits in the trellis state metric has (largely) different effect on the overall trellis decoding performance, we proposed an importance-aware clock skew scheduling technique that assigns those more important bits with longer timing slacks and hence better immunity to VOS-induced errors. This will provide system-level tolerance to VOS-induced errors in trellis decoders. With Viterbi and Max-Log-MAP decoders as test vehicles, we demonstrated that about 30% energy savings on trellis state metric computation can be realized with negligible decoding performance degradation","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":" 106","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120826534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
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