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2006 IEEE Workshop on Signal Processing Systems Design and Implementation最新文献

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Fault Tolerance of Quantized Unitary Precoders 量化酉预编码器的容错性
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352598
A. Y. Panah, R. Vaughan
{"title":"Fault Tolerance of Quantized Unitary Precoders","authors":"A. Y. Panah, R. Vaughan","doi":"10.1109/SIPS.2006.352598","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352598","url":null,"abstract":"Precoding based on channel state information (CSI) can help improve the performance of orthogonal space-time block codes (OSTBCs). Optimum precoders require a fairly detailed description of the channel singular vectors motivating the use of limited feedback communications to send some quantized form of the precoder to the transmitter. To this end, the singular value decomposition (SVD) is the fundamental step in extracting the singular vectors of the channel. In this paper we revisit a limited feedback technique based on the quantization of the dominant right singular vector of the channel matrix. Lifting the assumption of perfect channel estimation at the receiver, we investigate channels affected by Gaussian noise, line of sight component, and phase uncertainty. We also assume a more general channel model that incorporates channel correlations. Our simulations show that the quantized nature of the precoders provides the system with resiliency to such impairments","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115702575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Configuration and Representation of Large-Scale Dataflow Graphs using the Dataflow Interchange Format 使用数据流交换格式的大规模数据流图的配置和表示
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352547
I. Corretjer, Chia-Jui Hsu, S. Bhattacharyya
{"title":"Configuration and Representation of Large-Scale Dataflow Graphs using the Dataflow Interchange Format","authors":"I. Corretjer, Chia-Jui Hsu, S. Bhattacharyya","doi":"10.1109/SIPS.2006.352547","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352547","url":null,"abstract":"A wide variety of DSP design tools have been developed that incorporate dataflow graph representations into their GUI-based design environments. However, as the complexity of application graph topologies increases, textual manipulation of graph specifications becomes increasingly important. The dataflow interchange format (DIF) provides a text-based language for the description of dataflow graphs. Currently, the DIF infrastructure supports the specification of mixed-grain dataflow models, porting of dataflow applications specified in DIF across DSP design tools, software synthesis of applications specified in DIF, as well as a variety of optimization and analysis capabilities. This paper presents a novel set of dataflow graph configuration features that have been developed in the DIF language. These features greatly enhance the flexibility and power with which dataflow graphs, especially large-scale graphs, can be constructed and manipulated in DIF. To support the new graph configuration capabilities, several new concepts have been incorporated into the DIF language semantics, such as the capability to handle certain dynamic dataflow constructs, and support for C-like arrays in DIF specifications. Along with these concepts, a new framework for the construction and manipulation of DIF objects through the use of C/C++ is presented, and applications of this framework are demonstrated","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124981750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A Theoretical Model and Study of Weighted MCTF Residual Energy 加权MCTF剩余能的理论模型及研究
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352566
Fengling Li, N. Ling, Stephen A. Chiappari
{"title":"A Theoretical Model and Study of Weighted MCTF Residual Energy","authors":"Fengling Li, N. Ling, Stephen A. Chiappari","doi":"10.1109/SIPS.2006.352566","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352566","url":null,"abstract":"This paper presents a theoretical model and study of the impact of the weighted motion-compensated residual energy on the coding efficiency of motion-compensated temporal filtering (MCTF) when MCTF update steps are performed at both encoder and decoder sides and when update steps are executed at the encoder side only. We observe that in the presence of the uncompensated quantization errors due to the MCTF open-loop structure, the decoder must attempt to recover the update weight used by the encoder and this non-linear transform may contribute to the possible magnification of the quantization errors. We apply our analysis to the joint scalable video model (JSVM) 2.0. It is demonstrated that performing the MCTF update step at the decoder side does not contribute significantly to the coding efficiency, except at high spatial-temporal resolutions with high bit rates. This further justifies theoretically the elimination of the MCTF update step as a normative tool for temporal scalability in the current H.264/AVC scalable extension development","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116052411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A Reconfigurable SOS-based Rayleigh Fading Channel Simulator 一种可重构的基于sos的瑞利衰落信道模拟器
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352552
A. Alimohammad, B. Cockburn
{"title":"A Reconfigurable SOS-based Rayleigh Fading Channel Simulator","authors":"A. Alimohammad, B. Cockburn","doi":"10.1109/SIPS.2006.352552","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352552","url":null,"abstract":"A channel simulator is essential in the development and accurate performance evaluation of wireless systems. This paper presents an improved hardware implementation of a Rayleigh fading channel simulator that uses only 13% of the Xilinx Virtex2P XC2VP100-6 field-programmable gate array (FPGA) and operates at up to 210 MHz, generating 210 million accurately distributed and correlated complex fading coefficients per second. Our fading channel simulator is 506 times faster than a software-based simulator written in C running on a 3.4-GHz Pentium 4 processor. The fading channel simulator layout in 90-nm CMOS technology occupies 967 mum2 of silicon area when the operating rate target is 500 MHz","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121269451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
On the Effects of Colored Noise on the Performance of LDPC Codes 有色噪声对LDPC码性能的影响
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352586
S. Tehrani, B. Cockburn, S. Bates
{"title":"On the Effects of Colored Noise on the Performance of LDPC Codes","authors":"S. Tehrani, B. Cockburn, S. Bates","doi":"10.1109/SIPS.2006.352586","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352586","url":null,"abstract":"The class of low-density parity-check (LDPC) codes includes some of the most powerful capacity-approaching codes reported to date. As a result, LDPC codes have been considered for many new communication applications. However, a better understanding of the effects of the signal impairments that exist in such applications is required. In this paper, the performance of various LDPC codes, including recent candidate LDPC codes for 10GBASE-T Ethernet, in the presence of colored noise is evaluated and compared with the effects of conventional additive white Gaussian noise (AWGN). The colored noise models in this study include high-frequency and low-frequency additive colored Gaussian noise (ACGN), and 1/f noise. The results show that LDPC codes are more vulnerable to colored noise than to AWGN and as the correlation between noise samples becomes stronger, their performance becomes more degraded. However, at the same level of colored noise power, the performance is increasingly degraded as noise correlation is spread over more noise samples","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"637 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116476945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Lossless Compression Using Two-Level and Multilevel Boolean Minimization 使用两级和多级布尔最小化的无损压缩
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352571
Jeenong Yang, S. A. Savari, Oskar Mencercv
{"title":"Lossless Compression Using Two-Level and Multilevel Boolean Minimization","authors":"Jeenong Yang, S. A. Savari, Oskar Mencercv","doi":"10.1109/SIPS.2006.352571","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352571","url":null,"abstract":"There has been work considering the use of two-level Boolean minimization for lossless data compression. However, two-level Boolean minimization is known to be suboptimal for circuit design as it introduces an artificial restriction by representing the minimized expression in sum of product form. As the use of multilevel Boolean minimization can lead to improvements in chip area compared to circuits designed using two-level minimization, it is natural to investigate compression via multilevel Boolean minimization. We here develop a lossless compression algorithm using a multilevel Boolean minimizer. Contrary to our expectations, two-level minimization appears to be better suited for data compression. This is a result about the structural complexity in multilevel minimized circuits","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"277 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127664667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
FPGA Implementation of Pipelined Architecture for Optical Imaging Distortion Correction 光学成像畸变校正流水线结构的FPGA实现
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352578
L. Qiang, N. Allinson
{"title":"FPGA Implementation of Pipelined Architecture for Optical Imaging Distortion Correction","authors":"L. Qiang, N. Allinson","doi":"10.1109/SIPS.2006.352578","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352578","url":null,"abstract":"Fast and efficient operation is a major challenge for complex image processing algorithms executed in hardware. This paper describes novel algorithms for correcting optical geometric distortion in imaging systems, together with the architectures used to implement them in FPGA-based hardware. The proposed architecture produces a fast, almost real-time solution for the correction of image distortion implemented using VHDL with a single Xilinx FPGA XCS3 1000-4 device. Using dedicated SRLC16 shift registers to build the synchronous FIFOs is an ideal utilization of the device resources available. The experimental results show that the barrel distortion can be quickly corrected with a very low residual error. The design can also be applied to other imaging processing algorithms in optical systems","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131387129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP Decoding 用于Viterbi和Log-MAP解码的可重构应用专用指令集处理器
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352570
Timo Vogt, N. Wehn
{"title":"A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP Decoding","authors":"Timo Vogt, N. Wehn","doi":"10.1109/SIPS.2006.352570","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352570","url":null,"abstract":"Future mobile and wireless communications networks require flexible modem architectures with high performance. This paper presents a dynamically reconfigurable application specific instruction set processor (dr-ASIP) for the application domain of channel coding in wireless communications systems: FlexiTreP. It features Viterbi and Log-MAP decoding for support of binary convolutional codes and binary as well as duobinary turbo codes. The FlexiTreP can support more than 10 current wireless communication standards. Furthermore, its flexibility allows for adaptation to future systems. It consists of a specialized pipeline and a dedicated communication and memory infrastructure. Simulation and synthesis results obtained for Log-MAP and Viterbi applications demonstrate maximum throughput of 200 and 133 Mbps, respectively","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125481336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
SmartMIMO: Energy-Aware Adaptive MIMO-OFDM Radio Link Control for Wireless Local Area Networks SmartMIMO:用于无线局域网的能量感知自适应MIMO-OFDM无线电链路控制
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352616
B. Bougard, G. Lenoir, A. Dejonghe, L. Perre, F. Catthoor, W. Dehaene
{"title":"SmartMIMO: Energy-Aware Adaptive MIMO-OFDM Radio Link Control for Wireless Local Area Networks","authors":"B. Bougard, G. Lenoir, A. Dejonghe, L. Perre, F. Catthoor, W. Dehaene","doi":"10.1109/SIPS.2006.352616","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352616","url":null,"abstract":"Multiple-antenna techniques (MIMO) have been proposed to improve wireless links spectrum efficiency and/or robustness. There exists a fundamental tradeoff between potential spectrum efficiency and robustness increase. But these multiple-antenna techniques come with an overhead in power consumption due to the duplication of part of the transmitter and receiver front-ends. From a system perspective, one has to focus on performance versus power consumption tradeoff. In this paper, we derive SmartMIMO: an adaptive energy-aware link adaptation approach which, next to the modulation and code rate, decides on using either space-division multiplexing (increasing spectrum efficiency) or space-time coding (increasing robustness) to transmit a given packet on a given MIMO channel. Energy-efficiency is shown to be improved by up to 30% when compared to non-adaptive techniques while the average rate is improved by up to 50% when compared to single-antenna transmission","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123820443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Transparent Embedded Compression in Systems-on-Chip 片上系统的透明嵌入式压缩
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352591
A. K. Riemens, R. V. D. Vleuten, P. V. D. Wolf, G. Jacob, J. V. D. Waerdt, J. Janssen
{"title":"Transparent Embedded Compression in Systems-on-Chip","authors":"A. K. Riemens, R. V. D. Vleuten, P. V. D. Wolf, G. Jacob, J. V. D. Waerdt, J. Janssen","doi":"10.1109/SIPS.2006.352591","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352591","url":null,"abstract":"Bandwidth to off-chip memory is a scarce resource in complex systems-on-chip for embedded media processing. We apply embedded compression for bandwidth-hungry image processing functions in order to alleviate this bandwidth bottleneck. In our solution embedded compression is implemented as part of the system-on-chip infrastructure, fully transparent for the hardware and software image processing components. Hence it can be applied without requiring changes to these components. We present the compression algorithm and demonstrate that we achieve significant bandwidth reductions (20%-40%) for image data at acceptable cost (approximately 1 mm2 in 90 nm CMOS) while preserving high image quality","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125124617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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