{"title":"Low Complexity List Updating Circuits for List Sphere Decoders","authors":"Yuping Zhang, Jun Tang, K. Parhi","doi":"10.1109/SIPS.2006.352550","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352550","url":null,"abstract":"Sphere decoder has been introduced to the multiple-input-multiple-output (MIMO) communication systems, with which the maximum likelihood (ML) detection becomes feasible. In order to combine the sphere decoders with the outer channel code decoder, researchers have proposed to include a candidate list in the sphere decoder to provide soft information to the channel code decoder. This algorithm is called list sphere decoder (LSD). In the LSD, different from the conventional sphere decoder (CSD), the candidate list introduces significant hardware overhead. In this paper, we propose to use a tree-type comparator array, a link table and sublists to reduce the hardware complexity of inserting new candidates into the list. Combining these techniques, we can reduce the complexity by around 90% compared with the straightforward implementations","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116669398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A New Early Termination Scheme of Iterative Turbo Decoding Using Decoding Threshold","authors":"Fan-Min Li, Cheng-Hung Lin, A. Wu","doi":"10.1109/SIPS.2006.352561","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352561","url":null,"abstract":"Although many stopping methods of iterative decoding have been discussed in the literatures extensively, many of them only focus on the solvable decoding. In this paper, we propose a new early termination (ET) scheme based on the decoding threshold. Moreover, we proposed the cross-correlation measurement to predict the decoding threshold. The iterative decoding can stop in either high-SNR situation where the decoded bits are highly reliable (solvable decoding), or in low-SNR situation where the decoder already has no capability to decode (unsolvable decoding). At the same time, the receiver can send an automatic-repeat-request (ARQ) message to the transmitter in noise-seriously-coupling situation. Through simulations, the reduced iterations due to the ET scheme almost will not affect the SNR performance. Based on our analysis and simulation results, we can further modify the conventional GENIE chart. The ET property can help to either reduce the computational complexity or power consumptions in implementing the iterative decoding in DSP processors or VLSIs in mobile handsets","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116788779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Architecture-Aware LDPC Code Design for Software Defined Radio","authors":"Yuming Zhu, C. Chakrabarti","doi":"10.1109/SIPS.2006.352617","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352617","url":null,"abstract":"Low-density parity-check (LDPC) codes have been adopted in the physical layer of many communication systems because of their superior performance. The direct implementation of these codes onto an existing software defined radio (SDR) platform is likely to be inefficient. Our approach is to design the LDPC code to match the constraints imposed by the existing architecture, without compromising the communication performance. We present a procedure for architecture-aware code design that involves feature identification, code construction and verification. Details of the procedure for the case when the SDR platform is equipped with a multi-stage interconnection network (MIN) are presented. By analyzing the characteristics of the MIN, simple yet explicit constraints are derived and used in the code construction step. The resulting LDPC code can not only be mapped very efficiently onto the SDR platform but also has very good bit error rate (BER) performance","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133219010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"0.35 μm 22μW Multiphase Programmable Clock Generator for Circular Memory SC FIR Filter For Wireless Sensor Applications","authors":"R. Dlugosz, K. Iniewski, T. Talaśka","doi":"10.1109/SIPS.2006.352573","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352573","url":null,"abstract":"The paper presents the programmable multiphase clock generator for switched-capacitor finite impulse response (SC FIR) circular memory filters. The proposed programmable clock circuit enables easy division of such kind of filters into different orders smaller sections, which when connected in series, lead to increase in filter efficiency: reduction of chip area, power dissipation, and rising up of the speed. The proposed clock generator enables adjustment of the impulses width, that simplifies design process and leads to structure, which is more robust to process variation. The clock circuit realized in CMOS 0.35 μm technology, dissipates 22 μW from 2 V power supply","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131599522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Molecular quantum-dot cellular automata","authors":"C. Lent","doi":"10.1109/SIPS.2006.352542","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352542","url":null,"abstract":"Molecular electronics is commonly conceived as reproducing diode or transistor action at the molecular level. The quantum-dot cellular automata (QCA) approach offers an attractive alternative in which binary information is encoded in the configuration of charge among redox-active molecular sites. The Coulomb interaction between neighboring molecules provides device-device coupling. No current flow between molecules is required. We present an ab initio analysis of a simple molecular system which acts as a molecular QCA cell. The intrinsic bistability of the charge configuration results in dipole or quadrupole fields which couple strongly to the state of neighboring molecules. We show how logic gates can be implemented. We examine the role of the relaxation of nuclear coordinates in the molecular charge reconfiguration.","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117288392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Exploit Multiple-Domain Sparseness for HSDPA Chip Level Equalization in SDR: Algorithm and DSP Implementation","authors":"Min Li, B. Bougard, F. Catthoor","doi":"10.1109/SIPS.2006.352548","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352548","url":null,"abstract":"Chip level equalization has been proved as one of the key enabling technologies for HSDPA (high speed downlink packet access) receiver. Although many complicated algorithms (Kalman, etc.) have been reported to have great performance, their complexity and irregularity make it difficult to have efficient parallel software implementation. Targeting processor based SDR (software defined radio) platform, our goal is to design a practical HSDPA chip level equalizer having implementation cost as low as NLMS but offering considerable performance improvement over NLMS. Our proposal is based on the observations of multiple domain sparseness in cellular channel. The first observation is that the channel input response (CIR) has only a few significant taps. Although previous work exploits this for complexity reduction, we utilize it to improve the BER instead. The second observation is that the channel dynamics is not always significant, based on which we propose a feedback-control based technique to make the equalizer aware of the variation of channel dynamics. In addition, the equalizer becomes scalable in terms of quality-cost. By exploiting both of the aforementioned sparseness, the proposed HSDPA chip equalizer can significantly lower the BER error floor introduced by channel dynamics, so that more than 5 dB SNR gain can be achieved with the same implementation cost (by scalability) as NLMS. The design is demonstrated on TI TMS320C6711","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"230 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114587793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Geelen, Aris Ferentinos, F. Catthoor, Arnout Vandecappelle, G. Lafruit, T. Stouraitis, R. Lauwereins, D. Verkest
{"title":"Software-Controlled Scratchpad Mapping Strategies for Wavelet-Based Applications","authors":"B. Geelen, Aris Ferentinos, F. Catthoor, Arnout Vandecappelle, G. Lafruit, T. Stouraitis, R. Lauwereins, D. Verkest","doi":"10.1109/SIPS.2006.352609","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352609","url":null,"abstract":"A comparison is performed between a simple hardware-controlled cache mapping and a systematic, software-controlled scratchpad mapping of a two-dimensional, lifting-based wavelet transform, in the context of dynamic applications. In this context it is important for the application to optimally exploit the memory hierarchy under the dynamically varying memory availability. Contrary to expectations, the comparison shows the cache-based mapping to exhibit a lower miss rate. The reasons for these different results are examined and improvements for the systematic scratchpad mapping are proposed which would give it a 30% lower missrate performance for localized wavelet-based applications","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122011602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yuan Lin, S. Mahlke, T. Mudge, C. Chakrabarti, A. Reid, K. Flautner
{"title":"Design and Implementation of Turbo Decoders for Software Defined Radio","authors":"Yuan Lin, S. Mahlke, T. Mudge, C. Chakrabarti, A. Reid, K. Flautner","doi":"10.1109/SIPS.2006.352549","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352549","url":null,"abstract":"Software defined radio (SDR) is an emerging paradigm for wireless terminals, in which the physical layer of communication protocols is implemented in software rather than by ASICs. Many of the current and next generation wireless protocols include turbo coding because of its superior performance. However, turbo decoding is computationally intensive, and its low power implementations have typically been in ASICs. This paper presents a case study of algorithm-architecture co-design of turbo decoder for SDR. We present a programmable DSP architecture for SDR that includes a set of architectural features to accelerate turbo decoder computations. We then present a parallel window scheduling for MAX-Log-MAP component decoder that matches well with the DSP architecture. Finally, we present a software implementation of turbo decoder for W-CDMA on the DSP architecture and show that it achieves 2 Mbps decoding throughput","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125050353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}