Exploit Multiple-Domain Sparseness for HSDPA Chip Level Equalization in SDR: Algorithm and DSP Implementation

Abstract

Chip level equalization has been proved as one of the key enabling technologies for HSDPA (high speed downlink packet access) receiver. Although many complicated algorithms (Kalman, etc.) have been reported to have great performance, their complexity and irregularity make it difficult to have efficient parallel software implementation. Targeting processor based SDR (software defined radio) platform, our goal is to design a practical HSDPA chip level equalizer having implementation cost as low as NLMS but offering considerable performance improvement over NLMS. Our proposal is based on the observations of multiple domain sparseness in cellular channel. The first observation is that the channel input response (CIR) has only a few significant taps. Although previous work exploits this for complexity reduction, we utilize it to improve the BER instead. The second observation is that the channel dynamics is not always significant, based on which we propose a feedback-control based technique to make the equalizer aware of the variation of channel dynamics. In addition, the equalizer becomes scalable in terms of quality-cost. By exploiting both of the aforementioned sparseness, the proposed HSDPA chip equalizer can significantly lower the BER error floor introduced by channel dynamics, so that more than 5 dB SNR gain can be achieved with the same implementation cost (by scalability) as NLMS. The design is demonstrated on TI TMS320C6711