2006 IEEE Workshop on Signal Processing Systems Design and Implementation最新文献_第7页

A Reduced-Complexity, Scalable Implementation of Low Density Parity Check (LDPC) Decoder 一种低密度奇偶校验(LDPC)解码器的低复杂度、可扩展实现

2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352560

Yuming Zhu, Yanni Chen, D. Hocevar, M. Goel

引用次数: 3

Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems 数字信号处理系统高级合成的位宽优化

2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352595

Caaliph Andriamisaina, B. Gal, E. Casseau

引用次数: 3

Pipelined ALU for Signal Processing to Implement Interval Arithmetic 实现区间算术的信号处理流水线ALU

2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352562

Ruchir Gupte, W. Edmonson, S. Ocloo, W. Alexander

{"title":"Pipelined ALU for Signal Processing to Implement Interval Arithmetic","authors":"Ruchir Gupte, W. Edmonson, S. Ocloo, W. Alexander","doi":"10.1109/SIPS.2006.352562","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352562","url":null,"abstract":"There are many applications within digital signal processing (DSP) that require the user to know how various numerical errors (uncertainty) affect the result. This uncertainty is represented by replacing non-interval values with intervals. Since most DSPs operate in real time environments, fast processors are needed to implement interval arithmetic. The goal is to develop a platform in which interval arithmetic operations are performed at the same computational speed as present day signal processors. We have proposed a design for an interval based arithmetic logic unit (I-ALU) whose computational time for implementing interval arithmetic operations is equivalent to many digital signal processors. Many DSP and control applications require a small subset of arithmetic operations that must be computed efficiently. This design has two independent modules operating in parallel to calculate the lower bound and upper bound of the output interval. The functional unit of the ALU performs the basic fixed-point interval arithmetic operations of addition, subtraction, multiplication and the interval set operations of union and intersection. In addition, the ALU is optimized to perform dot products through the multiply-accumulate instruction. Division traditionally is not implemented on digital signal processors unless computed with a shift operation. In this design, division by shifting is implemented. The ALU is designed to have maximum throughput while minimizing area","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125425974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Semi-Blind Channel Estimation for OFDM using Least Squares 基于最小二乘的OFDM半盲信道估计

2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352574

Jarlath Ifiok Umoh, T. Ogunfunmi

引用次数: 0

Automated Architectural Exploration for Signal Processing Algorithms 信号处理算法的自动化架构探索

2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352594

R. Hourani, Ravi Jenkal, W. R. Davis, W. Alexander

{"title":"Automated Architectural Exploration for Signal Processing Algorithms","authors":"R. Hourani, Ravi Jenkal, W. R. Davis, W. Alexander","doi":"10.1109/SIPS.2006.352594","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352594","url":null,"abstract":"This paper presents a design environment for efficiently generating application-specific intellectual property (IP) cores for system level signal processing algorithms. We present our view of a framework that combines common electronic design automation (EDA) tools to alleviate the designer from manually constructing the hardware models and analyzing their performance. We use our framework to efficiently implement design optimizations that improve the performance of the overall hardware architectures. Our framework is well suited for designers with a range of signal processing and hardware expertise. Our framework generates the dedicated IP cores and estimates the performance such as area, critical path delay, and latency within seconds. Parts of our framework also compare different hardware designs for various digital signal processing (DSP) algorithms and allows the designer to make architectural decisions earlier in the hardware design process. We use a GUI-based framework invoked from MATLAB to automatically build and analyze the hardware designs. Our framework generates efficient hardware designs described in SystemC and Verilog code, along with the performance metrics for each architecture. We illustrate the use of our framework by exploring and analyzing architectural variations of two case studies: finite impulse response (FIR) filters and adaptive channel equalizers","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115293943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A Robust Band-Tracking Packet Detector (BT-PD) in OFDM-Based Ultra-Wideband Systems 基于ofdm的超宽带系统中鲁棒带跟踪包检测器(BT-PD)

2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352575

J. Lai, Chun-Yuan Chu, A. Wu, Wen-Chiang Chen

引用次数: 4

Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC Codes 准循环LDPC码的部分并行重叠和积解码器结构

2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352585

Ning Chen, Yongmei Dai, Zhiyuan Yan

引用次数: 12

Low Complexity Implementations of Sum-Product Algorithm for Decoding Low-Density Parity-Check Codes 低密度奇偶校验码译码和积算法的低复杂度实现

2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352592

Daesun Oh, K. Parhi

{"title":"Low Complexity Implementations of Sum-Product Algorithm for Decoding Low-Density Parity-Check Codes","authors":"Daesun Oh, K. Parhi","doi":"10.1109/SIPS.2006.352592","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352592","url":null,"abstract":"In this paper, we propose low complexity implementations of sum-product algorithm (SPA) for decoding low-density parity-check (LDPC) codes. The finite precision implementations for SPA have an important tradeoff between the decoding performance and hardware complexity caused by two dominant area consuming factors. One is the memory for updated messages storage and the other is the look-up table (LUT) for implementation of nonlinear function Psi(x). The proposed two types of variable quantization schemes result in significant reductions of LUT sizes. Computer simulation results indicate that the performance losses of SPA with reduced LUT by proposed schemes are less than 0.05 dB compared to that of SPA with original LUT. Moreover, the proposed implementation offers a large reduction in the finite wordlength for storage of updated messages using a kind of compression technique without performance losses. As a result, using the proposed implementation based on variable quantization scheme and data compression technique, the novel proposed implementation for SPA decoder architecture offers significant reductions of 75% and 33% in hardware complexities of LUT and memories, respectively, without significant performance degradations over conventional uniform quantization scheme. Furthermore, since each LUT with variable (6:3) quantization scheme II has only 8 entries, its hardware implementation can be replaced with a small combination circuit instead of readonly-memory (ROM) for LUT","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114680554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

EM-based Channel Estimation for Space Time Block Coded MIMO OFDM Systems 基于em的空时分组编码MIMO OFDM系统信道估计

2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352577

H. M. Karkhanechi, B. Levy

引用次数: 9

Simplified Criteria for Early Iterative Decoding Termination 早期迭代译码终止的简化准则

2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352583

Spyros Gidaros, Vassilis Paliouras

引用次数: 2