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2006 IEEE Workshop on Signal Processing Systems Design and Implementation最新文献

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A Low Cost Packet Detector in OFDM-Based Ultra-Wideband Systems 基于ofdm的超宽带系统中的低成本数据包检测器
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352576
J. Lai, Chun-Yuan Chu, A. Wu, Wen-Chiang Chen
{"title":"A Low Cost Packet Detector in OFDM-Based Ultra-Wideband Systems","authors":"J. Lai, Chun-Yuan Chu, A. Wu, Wen-Chiang Chen","doi":"10.1109/SIPS.2006.352576","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352576","url":null,"abstract":"Multiband orthogonal frequency-division multiplexing (MB-OFDM) systems employ frequency-hopping technology to achieve the capabilities of multiple access and frequency diversity. However, they also complicate packet detector (PD) in terms of the requirement for the high hardware complexity. In this paper, we propose several low-cost design schemes for the PD, such as Walsh-Hadamard decomposition, buffered summation, and sign-bit-remaining methods. The estimated gate count of the resulting implemented PD is less than half that of existing solutions","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124722559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An Efficient Data Reuse Motion Estimation Engine 一种高效的数据重用运动估计引擎
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352613
S. Goel, Y. Ismail, Parimal Devulapalli, J. McNeely, M. Bayoumi
{"title":"An Efficient Data Reuse Motion Estimation Engine","authors":"S. Goel, Y. Ismail, Parimal Devulapalli, J. McNeely, M. Bayoumi","doi":"10.1109/SIPS.2006.352613","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352613","url":null,"abstract":"We present a novel motion estimation engine (MEE) architecture that efficiently reuses search area data while fully utilizing the hardware resources. A 2-D processing element (PE) core is central to the architecture. Search area data flows both horizontally as well as vertically while the current block data is stationary. A clever PE design ensures simple but highly regular dataflow through the core avoiding long interconnect delays. For a search range of [-16,+15] and block size of 16, our architecture can perform motion estimation for 60 fps of 4CIF video at 100 MHz","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115031350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
An Optimal Adaptive M-PSK Carrier Phase Detector Suitable for Fixed-Point Hardware Implementation within FPGAs and ASICs 适合fpga和asic内定点硬件实现的最优自适应M-PSK载波鉴相器
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352587
Y. Linn
{"title":"An Optimal Adaptive M-PSK Carrier Phase Detector Suitable for Fixed-Point Hardware Implementation within FPGAs and ASICs","authors":"Y. Linn","doi":"10.1109/SIPS.2006.352587","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352587","url":null,"abstract":"In this paper we shall present an NDA (non data aided) adaptive carrier phase detector for coherent M-PSK receivers operating in AWGN (additive white Gaussian noise). It shall be shown that the detector allows the carrier synchronization PLL (phase locked loop) to achieve optimal performance during both the acquisition and tracking operation modes. The conditions necessary for this optimatity to be achieved will be discussed, and it shall be shown that they are quite reasonable and allow the proposed detector to be implemented in many contemporary M-PSK receivers. The optimal behaviour of the PLL will be shown to bold regardless of the SNR (signal-to-noise ratio) and of the AGC (automatic gain control) circuit behaviour. Moreover, the proposed detector has a simple fixed-point structure that can be feasibly implemented using few hardware resources within contemporary FPGAs (field programmable gate arrays) or ASICs (application specific integrated circuits). Finally, operation of the proposed detector under frequency-flat slow signal fading conditions is also discussed","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"256 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132044815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering Systems 在线MSR-CORDIC VLSI架构及其在低成本旋转自适应滤波系统中的应用
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352620
T. Yu, Chi-Li Yu, Kai-Yuan Jheng, A. Wu
{"title":"On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering Systems","authors":"T. Yu, Chi-Li Yu, Kai-Yuan Jheng, A. Wu","doi":"10.1109/SIPS.2006.352620","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352620","url":null,"abstract":"A novel on-line mixed-scaling-rotation CORDIC (MSR-CORDIC) VLSI architecture is proposed. This architecture not only maintains the scaling-free property of the original MSR-CORDIC, but also achieves the target of on-line angle computation. Compared with other existing CORDIC solutions, the proposed architecture is faster and more cost-efficient, especially for QRD-RLS filtering systems. Moreover, this on-line MSR-CORDIC can also be adopted by other rotation-based DSP applications","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"30 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132570951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Efficient Memory Reuse and Sub-Pixel Interpolation Algorithms for ME/MC of H.264/AVC
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352612
C. Hyun, S. D. Kim, M. Sunwoo
{"title":"Efficient Memory Reuse and Sub-Pixel Interpolation Algorithms for ME/MC of H.264/AVC","authors":"C. Hyun, S. D. Kim, M. Sunwoo","doi":"10.1109/SIPS.2006.352612","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352612","url":null,"abstract":"This paper presents efficient memory reuse and sub-pixel interpolation algorithms for ME (motion estimation)/MC (motion compensation) of H.264/AVC ME is a computationally intensive task and its number of memory accesses is quite high. Moreover, sub-pixel interpolation requires many additions and multiplications. The proposed memory reuse algorithm utilizes the position similarity of the MVp (motion vector prediction) among neighboring Sub-MBs (macro blocks). It can reduce a large number of memory accesses and can save power consumption by sharing SR (search range) of the current block. In addition, simplifying weights of sub-pixel interpolation can eliminate multiplications. Thus, this algorithm can reduce its complexity and power consumption. Therefore, the proposed memory reuse and sub-pixel interpolation algorithms can be employed for low power video compression","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129398696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Spatial Optical Distortion Correction in an FPGA 基于FPGA的空间光畸变校正
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352593
L. Qiang, N. Allinson
{"title":"Spatial Optical Distortion Correction in an FPGA","authors":"L. Qiang, N. Allinson","doi":"10.1109/SIPS.2006.352593","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352593","url":null,"abstract":"Due to the complexities of the image processing algorithms, correcting spatial distortion of optical images quickly and efficiently is a major challenge. This paper describes an efficient pipelined parallel architecture for optical distortion correction in imaging systems using a low cost FPGA device. The proposed architecture produces a fast, almost realtime solution for the correction of image distortion implemented using VHDL HDL with a single Xilinx FPGA XCS31000-4 device. The experimental results show that the barrel and pincushion distortion can be corrected with a very low residual error. The system architecture can be applied to other imaging processing algorithms in optical systems","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134523329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automated derivation of NoC Communication Specifications from Application Constraints 从应用约束中自动派生NoC通信规范
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352588
S. Evain, J. Diguet, M. E. Khodary, D. Houzet
{"title":"Automated derivation of NoC Communication Specifications from Application Constraints","authors":"S. Evain, J. Diguet, M. E. Khodary, D. Houzet","doi":"10.1109/SIPS.2006.352588","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352588","url":null,"abstract":"This paper focuses on the highest step of our NoC design flow, which addresses the efficient deployment of real applications over an ad hoc NoC. At this level we propose a methodology and a tool to decide the NoC parameters and to generate the path coding within network interfaces for guarantied and best effort communications. The originality of our approach is based on two points. First our tool includes a derivation technique to obtain NoC communication constraints (latency, bandwidth) from application designer knowledge (application throughput). Secondly, the decision tool explores a 3D graph (t,x,y) for path allocation while taking into account mutual exclusion and global latency for FIFO minimisation under time constraints. This paper illustrates the first point. Two real applications: smart camera and multiprocessor turbo-decoder are presented to illustrate the design flow","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125105925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Maximum Likelihood Estimation of Carrier Frequency Offset in Correlated MIMO OFDM Systems 相关MIMO OFDM系统中载波频偏的最大似然估计
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352554
X. Zeng, A. Ghrayeb
{"title":"Maximum Likelihood Estimation of Carrier Frequency Offset in Correlated MIMO OFDM Systems","authors":"X. Zeng, A. Ghrayeb","doi":"10.1109/SIPS.2006.352554","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352554","url":null,"abstract":"This paper discusses maximum likelihood (ML) carrier frequency offset (CFO) estimation based on virtual subcarriers for multiple-input multiple-output (MIMO) systems employing orthogonal frequency division multiplexing (OFDM) over Rayleigh fading channels. In our ML approach, the channel and data are treated as random variables, unlike existing ML approaches in which the channel and data are treated as unknown constants. This in turn enables us to incorporate the spatial correlation and transmit data correlation into the analysis. In particular, we derive closed-form cost functions which can be used to accurately estimate the CFO. We also derive the Cram r-Rao lower bounds (CRLBs) for these estimators. We show that the presence of these correlations does not impact the CFO estimation significantly, especially at high signal-to-noise ratio. We present several examples to support the analysis","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115570097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fixed-to-Variable Length Source Coding Using Turbo Codes 使用Turbo码的固定到可变长度的源编码
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352584
J. Haghighat, W. Hamouda, M. Soleymani
{"title":"Fixed-to-Variable Length Source Coding Using Turbo Codes","authors":"J. Haghighat, W. Hamouda, M. Soleymani","doi":"10.1109/SIPS.2006.352584","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352584","url":null,"abstract":"Lossless turbo source coding with decremental redundancy is an effective approach for compressing binary sources. A large block length lossless turbo source encoder offers compression rates close to the source entropy, but with large latency. In this note, we propose a lossless compression technique for binary memory less sources using short block length turbo codes. To achieve compression rates close to the source entropy, we modify different components of the encoder. We focus on the design of the parity interleaver for different compression rates. Also, we replace the square shape puncturing array with a rectangular shape array that allows finer puncturing and hence improved compression rates. Finally, instead of a single code, we employ many codes operating in parallel. Given these modifications, we evaluate the encoding complexity of the proposed code","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115623943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
VSIP : Video Specific Instruction Set Processor for H.264/AVC VSIP: H.264/AVC视频专用指令集处理器
2006 IEEE Workshop on Signal Processing Systems Design and Implementation Pub Date : 2006-10-01 DOI: 10.1109/SIPS.2006.352567
K. Lee, S. D. Kim, M. Sunwoo
{"title":"VSIP : Video Specific Instruction Set Processor for H.264/AVC","authors":"K. Lee, S. D. Kim, M. Sunwoo","doi":"10.1109/SIPS.2006.352567","DOIUrl":"https://doi.org/10.1109/SIPS.2006.352567","url":null,"abstract":"H.264/AVC adopts new features compared with previous multimedia algorithms. It is inefficient to implement some of the new features with existing DSP instructions. This paper presents an application specific instruction set processor (ASIP) for implementation of H.264/AVC, called VSIP. The proposed VSIP has novel instructions for new features, such as intra prediction, deblocking filter, integer transform, etc. In addition, VSIP employs hardware accelerators for inter prediction and entropy coding. Performance comparisons show a significant improvement compared with existing DSPs. Moreover, the proposed hardware accelerators have small size and can support real-time video processing. The results indicate that VSIP is one of promising solutions for H.264/AVC","PeriodicalId":319147,"journal":{"name":"2006 IEEE Workshop on Signal Processing Systems Design and Implementation","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115691473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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