Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.最新文献_第6页

High speed synchronization module implemented in altera stratix II FPGA 在altera stratix II FPGA上实现高速同步模块

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706540

K. Przygoda, M. Grecki

引用次数: 0

High-precision Low-power Voltage Follower For Hardware Signal Processing 用于硬件信号处理的高精度低功率电压从动器

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706589

R. Wojtyna

{"title":"High-precision Low-power Voltage Follower For Hardware Signal Processing","authors":"R. Wojtyna","doi":"10.1109/MIXDES.2006.1706589","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706589","url":null,"abstract":"A specific application CMOS voltage follower is presented, which is well suited to be used as a component of VLSI analog electronics such as hardware implemented artificial neural networks (ANN's) or switched-capacitor filters (SC-filters). The main advantages of the follower are: a very high precision of operation and low power consumption. Another advantage is a low input capacitance (about 2fF) and extremely high input resistance. Compared with general purpose followers, its disadvantage is a restricted range of input voltage variations. This is the price we pay for the achieved positive features. Apart from the general idea and some previous versions of the follower, a new circuit realization is presented. SPICE simulation results concerning layouts made for a 0.35mum CMOS process are shown. These results are in good agreement with theoretical predictions as well as experimental results achieved for a 0.8mum prototype. Prototypes designed for the 0.18mum technology are currently being fabricated (in cooperation with University of Alberta in Canada) and no measurements have been performed yet","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121304141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Design Of Decimation Filter For Multibit Sigmadelta Modulator With Two-step Quantization 两步量化多比特信号调制器的抽取滤波器设计

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706663

A. Kuncheva, L. Fujcik, T. Mougel, B. Donchev, M. Hristov

引用次数: 2

New Ultra Low Power Switched - Current Finite Impulse Response Filters Realized In Cmos 0.18 /spl mu/m Technology Cmos 0.18 /spl mu/m技术实现的新型超低功耗开关电流有限脉冲响应滤波器

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706595

R. Dlugosz

{"title":"New Ultra Low Power Switched - Current Finite Impulse Response Filters Realized In Cmos 0.18 /spl mu/m Technology","authors":"R. Dlugosz","doi":"10.1109/MIXDES.2006.1706595","DOIUrl":"https://doi.org/10.1109/MIXDES.2006.1706595","url":null,"abstract":"New switched current (SI) finite impulse response (FIR) filter structures are presented in this work. In FIR filters signal samples stored in delay line are multiplied by coefficients and then summed. Those three basic operations can be realized in different ways for both digital and analog signals. SI FIR filter structures proposed here operate in current mode, what means that both input and output signals are currents and all analog building blocks work in current domain. Samples are stored in current mode sample-and-hold elements, multiplication by coefficients is realized in current-mirrors, and summing in output junction. Proposed filters do not use op amps, thus consuming very low power, what is the main assumption here. On the basis of proposed structures filter banks can be easily realized. An example 7th-order filter with equal coefficients was realized in CMOS 0.18 mum technology and is described in the paper. Parameters of this circuit are very promising: chip area is 5000 mum2, power consumption is 150 nW from 0.5 V voltage supply. Low-power clock generator is used in the filter. Designed filter works with clock frequency up to 5 MHz. Attenuation in the stopband is below 40 dB, what is sufficient for many wireless sensor networks (WSN) applications","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134411752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Partial Analysis For Functional Testing Of Digital IP-cores 数字ip核功能测试的部分分析

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706648

H. Kadim

引用次数: 0

Empirical model of skew in clock-distribution grids 时钟配电网偏态的经验模型

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706623

D. Kasprowicz

引用次数: 0

Scaling Rules For Mos Analog Design Reuse 大多数模拟设计重用的缩放规则

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706603

T. Levi, N. Lewis, J. Tomas, P. Fouillat

引用次数: 11

Temperature effect on the buried double junction color detector behavior 温度对埋置双结彩色探测器性能的影响

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706548

F. Haned, M. B. Chouikha, G. Alquié

引用次数: 1

Analysis And Design Of Ptat Temperature Sensor In Digital CMOS VLSI Circuits 数字CMOS VLSI电路中温度传感器的分析与设计

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706612

A. Golda, A. Kos

引用次数: 16

Offset Loopback Test For IC RF Transceivers 对IC射频收发器的偏移环回测试

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI: 10.1109/MIXDES.2006.1706647

J. Dabrowski, R. Ramzan

引用次数: 13