2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors最新文献

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Characterization of deformation induced by micro-second laser anneal using CGS interferometry 用CGS干涉法表征微秒激光退火引起的变形
D. Owen, Yun Wang, A. Hawryluk, Senquan Zhou, J. Hebb
{"title":"Characterization of deformation induced by micro-second laser anneal using CGS interferometry","authors":"D. Owen, Yun Wang, A. Hawryluk, Senquan Zhou, J. Hebb","doi":"10.1109/RTP.2008.4690546","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690546","url":null,"abstract":"The understanding and control of mechanical stresses accumulated during device fabrication is becoming more critical at advanced technology nodes. For example, e-SiGe is being used more and more extensively to strain the channel and improve PMOS performance. However, increases in Ge concentration result in increased susceptibility to strain relaxation and severe wafer deformation during advanced thermal processing. As a result, the precise control of the stress induced during annealing is becoming increasing important. This paper describes the use of a stress measurement technology, the Coherent Gradient Sensing (CGS) interferometer, for the characterization of deformation induced during micro-second laser annealing. The unique features of the CGS technique enable not only the characterization of the magnitude of wafer bow and warp, but the local uniformity of strain relaxation. Results are presented showing the relationship between wafer deformation and the fundamental parameters of micro-second laser annealing. In addition, the effects of processing history on laser anneal-induced deformation will also be evaluated, and techniques for managing stress accumulation across an entire process flow will be discussed.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123046037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Quality and reliability of oxide by low thermal budget rapid thermal oxidation 低热收支快速热氧化法提高氧化物的质量和可靠性
Yonah Cho, Yoshitaka Yokota, C. Olsen, A. Tjandra, Kai Ma, Vicky Nguyen
{"title":"Quality and reliability of oxide by low thermal budget rapid thermal oxidation","authors":"Yonah Cho, Yoshitaka Yokota, C. Olsen, A. Tjandra, Kai Ma, Vicky Nguyen","doi":"10.1109/RTP.2008.4690559","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690559","url":null,"abstract":"In order to meet increasing requirement for low thermal budget oxidation in memory and logic applications, RadOx™, previously known as in-situ steam generation (ISSG) oxidation, processes of low thermal budgets were developed. In this paper, oxides obtained by 700°C soak and 900–1050°C spike RadOx™ processes are presented. Sidewall growth behavior in STI-type structures were characterized and showed no bird’s beak encroachment by the developed oxidation processes. Basic bulk oxide (40Å) integrity and reliability characteristics were compared to the 1050°C soak RadOx™ reference. Using planar metal-on-semiconductor (MOS) capacitors as the test vehicles, flat-band voltage (V<inf>fb</inf>), interface trap density (D<inf>it</inf>), leakage current, and stress-induced leakage current (SILC) were measured. V<inf>fb</inf> shift of less than 20mV and D<inf>it</inf> less than 2×10<sup>11</sup>/cm<sup>2</sup> were observed from the low temperature soak and spike oxides. Leakage currents from fresh devices and after high current stressing (0.1A/cm<sup>2</sup>) were comparable to the reference oxide.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"266 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123290951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Total temperature fluctuation of a patternned wafer in the millisecond annealing 微秒退火过程中图像化晶片的总温度波动
T. Kubo, T. Sukegawa, M. Kase
{"title":"Total temperature fluctuation of a patternned wafer in the millisecond annealing","authors":"T. Kubo, T. Sukegawa, M. Kase","doi":"10.1109/RTP.2008.4690555","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690555","url":null,"abstract":"This paper describes the total temperature fluctuation within patterned wafers based on sub-100μm-scaled microscopic temperature non-uniformity within a chip, and mm-scaled macroscopic temperature variation within blanket wafers in laser spike annealing (LSA) and Flash Lamp Annealing (FLA). Temperature distribution within a chip and non-uniformity within blanket wafers are obtained by thermal wave (TW) method and conventional 4 point probe sheet resistance measurement, respectively. In the case of LSA, it was found that the local temperature is less dependent on pattern density. However, hot spots which local temperature is 50 °C higher than the surrounding area occur near large active areas. In the case of FLA, the local temperature depends strongly on pattern pitch. We did not find the hot spot. Total temperature fluctuations of pattern wafers of LSA and FLA reach about 90 and 120 °C.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122335992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Si surface preparation and passivation by vapor phase of heavy water 重水气相法制备硅表面及钝化
Andrea Edit Pap, P. Petrik, B. Pécz, G. Battistig, I. Bársony, Zsolt Szekrényes, K. Kamarás, Z. Schay, Z. Nényei
{"title":"Si surface preparation and passivation by vapor phase of heavy water","authors":"Andrea Edit Pap, P. Petrik, B. Pécz, G. Battistig, I. Bársony, Zsolt Szekrényes, K. Kamarás, Z. Schay, Z. Nényei","doi":"10.1109/RTP.2008.4690558","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690558","url":null,"abstract":"In our previously published paper [1, 2] we demonstrated that deuterium adsorbs on Si surface at room temperature much stronger than hydrogen [3, 4]. Moreover, in case of deuterium passivated wafers the vacuum storage can be omitted without risking the non-controlled native oxidation of silicon for up to 5 hours or more. It could be a suitable and more robust surface cleaning and passivation process for the industry, but heavy water is expensive. As a cheaper procedure, we present in this paper the results of our studies in which the Si surface is treated in vapor phase of heavy-water (D2O) + 50% HF (e.g. 20:1) mixture at 25, 40, 50 and 65 °C, for 1, 10 and 60 minutes. The surface evolution of the D-passivated surface was followed by contact angle measurements, by spectroscopic ellipsometry (SE), by atomic force microscopy (AFM), by X-ray photoelectron spectroscopy (XPS), by transmission electron microscopy (TEM) and by infrared absorption spectroscopy (IR) qualification and the results were compared to the H-passivated Si surface. It turned out that 1 min vapor phase treatment at 65 °C was enough to remove the native oxide and to passivate the Si surface without any degradation of the atomic surface flatness. Combination of D (or H) passivation with rapid thermal process (RTP) based on the thermal desorption kinetics of the adsorbed D and/or H layers on Si is a promising method for improved interface engineering and for better initial reactions in case of ultra thin dielectric layer formations.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130681414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Control of laser induced interface traps with in-line corona charge metrology 用在线电晕电荷测量法控制激光诱导界面陷阱
J. Everaert, E. Rosseel, C. Ortolland, M. Aoulaiche, T. Hoffmann, T. Pavelka, E. Don
{"title":"Control of laser induced interface traps with in-line corona charge metrology","authors":"J. Everaert, E. Rosseel, C. Ortolland, M. Aoulaiche, T. Hoffmann, T. Pavelka, E. Don","doi":"10.1109/RTP.2008.4690551","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690551","url":null,"abstract":"Laser annealing is an ideal activation step for ultra shallow junctions (USJ). But it can increase the density of interface traps (Dit) of the gate dielectric, resulting in degraded NBTI reliability. Therefore the influence of anneal conditions is studied with corona charge metrology. SiO2 is used as a reference gate dielectric for which recovery solutions are worked out to reduce the laser induced Dit. But, on the other hand, the recovery can cause degradation of the USJ, limiting the choice of process conditions for recovery. The reduction in Dit by spike anneal can be explained by stress relaxation in case of SiO2 and SiON. For HiK gate dielectrics the behaviour is more complex due to possible chemical interactions and crystallization. Recovery can be done by spike anneal and mulitscan laser anneal. The latter is better towards USJ properties.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132362487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Channel strain engineering for high performance CMOS technology 高性能CMOS技术的通道应变工程
H. Nayfeh
{"title":"Channel strain engineering for high performance CMOS technology","authors":"H. Nayfeh","doi":"10.1109/RTP.2008.4690531","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690531","url":null,"abstract":"▪ Longitudinal compressive stress in the GPa regime is required for the 45nm SOI high-performance pFET device to meet aggressive performance goals. ▪ Compressive stress liner, and eSiGe stressor enhancement was employed in order to achieve a 1.6 GPa channel stress level. ▪ Mobility enhancement of the 45nm baseline device is shown to be 4X-fold higher than relaxed-Si. Effective piezo-cofficients extracted for wide range of stress highlighting 3 stress regimes. Stress and drive current are shown to be correlated with a coefficient equal to ∼ 0.25. ▪ Low-field mobility is shown to be strongly correlated to injection velocity. High strain pFET devices with gate length down to 35nm operate at about 60% of the thermal limit. ▪ Challenge for future technology nodes- the mobility vs stress relationship for channel stress levels in the 1.6GPa regime is approaching saturation. To continue this incredible rate of performance increase (17%/year), methods of increasing the low-field mobility through increased thermal velocity is required.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116755488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Basic strain physics 基本应变物理
S. T. Chang, C. Liu
{"title":"Basic strain physics","authors":"S. T. Chang, C. Liu","doi":"10.1109/RTP.2008.4690530","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690530","url":null,"abstract":"•The basic strain physics behind the CMOS device is explained and future cases of technological importance to the industry are introduced. •Strain Engineering offers very large improvements in nanoscale MOSFETs and is scalable to the end of the Si CMOS roadmap. •Strain combined with new channel material such as Ge has a bright future and can enhance CMOS technology.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133385693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Si spontaneous emission during RTP and its impact on low-temperature pyrometry RTP过程中硅的自发发射及其对低温热分析的影响
J.P. Li, A. Hunter, Rajesh Ramanujam
{"title":"Si spontaneous emission during RTP and its impact on low-temperature pyrometry","authors":"J.P. Li, A. Hunter, Rajesh Ramanujam","doi":"10.1109/RTP.2008.4690564","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690564","url":null,"abstract":"Si fluorescence or spontaneous emission was discovered during the development of lower-temperature pyrometer. To reveal unambiguously the Si spontaneous emission, a high-power 980nm laser is used together with a high sensitivity IR spectrometer. Clear Si fluorescence spectra with peaks at ∼1140nm were obtained at different Si temperatures. The Si fluorescence peaks shift to longer wavelength, in agreement with Si bandgap narrowing with increasing temperatures. Wafers of different doping levels and types were studied for Si spontaneous emission. It is found that lightly doped (resisitivity ≪20 ohms-cm) Si has the highest level of Si spontaneous emission. On the other hand, heavily doped Si does not generate any Si spontaneous emission, mainly due to the higher recombination. Since the Si spontaneous emission has a broad spectrum, it spills into the RTP pyrometer spectral bandwidth and acts as s spurious pyrometer signal. Even though Si has very low efficiency for light emission due to its indirect bandgap, the fluorescence emitted light is still on the level of pyrometer signal equivalent to ∼200 to 250C.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122903909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low temperature microwave annealing of S/D S/D的低温微波退火
B. Lojek
{"title":"Low temperature microwave annealing of S/D","authors":"B. Lojek","doi":"10.1109/RTP.2008.4690556","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690556","url":null,"abstract":"Microwave annealing of ion-implanted layers in semiconductors is an emerging application of thermal processing of semiconductors, with low processing temperature eliminating unwanted diffusion as the main potential advantage. In this work, requirements and limitations of the microwave processing chamber are discussed first, and secondly, for the first time, results from a processed manufacturing lot using microwave annealing are discussed. The achieved results show that is feasible to achieve the same level of activation of implanted layers as in conventional high temperature RTP processing using the microwave at temperatures below 400 °C, and equivalent processing time.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123000341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
High-performance bulk CMOS technology with millisecond annealing and strained Si 采用毫秒退火和应变Si的高性能块体CMOS技术
T. Sugii, K. Ikeda, T. Miyashita
{"title":"High-performance bulk CMOS technology with millisecond annealing and strained Si","authors":"T. Sugii, K. Ikeda, T. Miyashita","doi":"10.1109/RTP.2008.4690536","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690536","url":null,"abstract":"High-performance planar, bulk CMOS technology for 45nm nodes and beyond is reviewed from the point of mobility enhancement techniques and millisecond annealing techniques. Through continuous efforts to increase on-current with the strained techniques while scaling transistor dimensions with millisecond annealing, competitive high-end CMOS technology for 45nm node was realized.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129240236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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