High-performance bulk CMOS technology with millisecond annealing and strained Si

Abstract

High-performance planar, bulk CMOS technology for 45nm nodes and beyond is reviewed from the point of mobility enhancement techniques and millisecond annealing techniques. Through continuous efforts to increase on-current with the strained techniques while scaling transistor dimensions with millisecond annealing, competitive high-end CMOS technology for 45nm node was realized.