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2011 21st International Conference on Field Programmable Logic and Applications最新文献

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An FPGA Solver for SAT-Encoded Formal Verification Problems sat编码形式验证问题的FPGA求解器
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.18
K. Kanazawa, T. Maruyama
{"title":"An FPGA Solver for SAT-Encoded Formal Verification Problems","authors":"K. Kanazawa, T. Maruyama","doi":"10.1109/FPL.2011.18","DOIUrl":"https://doi.org/10.1109/FPL.2011.18","url":null,"abstract":"Formal verification is one of the most important applications of the satisfiability (SAT) problem. WSAT and its variants are one of the best performing stochastic local search algorithms. In this paper, we propose an FPGA solver for SAT-encoded verification problems based on a WSAT algorithm. The size of the verification problems is very large, and most of the data used in the algorithm have to be placed in off-chip DRAMs. The performance of the solver is limited by the throughput and access delay of the DRAMs, not by the parallelism in FPGA. We show how much speed-up is possible under this situation using the memory throughput, memory access delay and the operational frequency of FPGA as parameters.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115307798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Optimizing an Open-Source Processor for FPGAs: A Case Study 优化fpga的开源处理器:一个案例研究
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.107
L. Barthe, L. Cargnini, P. Benoit, L. Torres
{"title":"Optimizing an Open-Source Processor for FPGAs: A Case Study","authors":"L. Barthe, L. Cargnini, P. Benoit, L. Torres","doi":"10.1109/FPL.2011.107","DOIUrl":"https://doi.org/10.1109/FPL.2011.107","url":null,"abstract":"Optimizing a processor for FPGA architectures is a challenging task. In this paper, we attempt to bridge the performance gap between commercial and open-source processors by introducing various design and implementation strategies at the register transfer abstraction level, where most optimizations require several design trade-offs to ensure an efficient and proper use of available resources. Using an open-source processor as a case study, we demonstrate the effectiveness of the proposed methods through a set of synthesis and benchmark results.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115435159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Radix Tree Router for Scalable FPGA Networks 用于可扩展FPGA网络的基数树路由器
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.24
William V. Kritikos, Y. Rajasekhar, A. Schmidt, R. Sass
{"title":"A Radix Tree Router for Scalable FPGA Networks","authors":"William V. Kritikos, Y. Rajasekhar, A. Schmidt, R. Sass","doi":"10.1109/FPL.2011.24","DOIUrl":"https://doi.org/10.1109/FPL.2011.24","url":null,"abstract":"Many FPGA based Network-on-Chip (NoC) and directly connected clusters use routers implemented in the FPGA fabric. Existing projects have optimized the routers for low resource utilization, low latency, and high bandwidth, often at the cost of programmability and manageability. Developers using the existing FPGA networks often have no way to specify a source or destination of a message except by using the physical locations of the nodes in the network. This low level of abstraction limits developer productivity and the ability of the network to adapt to changing conditions. We present an FPGA network that resolves these issues by allowing the developer to use familiar 32-bit addresses similar to an IP address and a router that uses a software managed routing table. The implementation presented here demonstrates similar resource utilization and bandwidth with a minimal increase in latency when compared to existing FPGA router implementations.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121817016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High Frequency Trading Acceleration Using FPGAs 使用fpga的高频交易加速
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.64
Christian Leber, Benjamin Geib, Heiner Litz
{"title":"High Frequency Trading Acceleration Using FPGAs","authors":"Christian Leber, Benjamin Geib, Heiner Litz","doi":"10.1109/FPL.2011.64","DOIUrl":"https://doi.org/10.1109/FPL.2011.64","url":null,"abstract":"This paper presents the design of an application specific hardware for accelerating High Frequency Trading applications. It is optimized to achieve the lowest possible latency for interpreting market data feeds and hence enable minimal round-trip times for executing electronic stock trades. The implementation described in this work enables hardware decoding of Ethernet, IP and UDP as well as of the FAST protocol which is a common protocol to transmit market feeds. For this purpose, we developed a microcode engine with a corresponding instruction set as well as a compiler which enables the flexibility to support a wide range of applied trading protocols. The complete system has been implemented in RTL code and evaluated on an FPGA. Our approach shows a 4x latency reduction in comparison to the conventional Software based approach.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"2004 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127319429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 63
Implementation in FPGA of Address-Based Data Sorting 基于地址的数据排序的FPGA实现
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.81
V. Sklyarov, I. Skliarova, D. Mihhailov, A. Sudnitson
{"title":"Implementation in FPGA of Address-Based Data Sorting","authors":"V. Sklyarov, I. Skliarova, D. Mihhailov, A. Sudnitson","doi":"10.1109/FPL.2011.81","DOIUrl":"https://doi.org/10.1109/FPL.2011.81","url":null,"abstract":"The paper describes the hardware implementation and optimization of sorting algorithms that use data items as memory addresses with one-bit flags indicating presence of data. The proposed technique enables such type of address-based sorting to be applied either directly or through tree-walk tables permitting number of bits in sorted data items to be increased by constructing and traversing N-ary trees (N>2) composed of so called no-match and working nodes. The latter are organized in well balanced sub-trees of equal depth. It is allowed more than one data item to be assigned to leaves of working sub-trees and such sets of items are processed by fast acceleration circuits. Experiments and comparisons demonstrate that the proposed technique can be used efficiently in low cost FPGAs.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115577143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Capacitive Boosting for FPGA Interconnection Networks FPGA互连网络的电容增强
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.89
F. Eslami, M. Sima
{"title":"Capacitive Boosting for FPGA Interconnection Networks","authors":"F. Eslami, M. Sima","doi":"10.1109/FPL.2011.89","DOIUrl":"https://doi.org/10.1109/FPL.2011.89","url":null,"abstract":"FPGA interconnection network is implemented using nMOS pass transistor multiplexers. Since the threshold voltage drop across an nMOS device degrades the high logic value, the pMOS transistors of the downstream buffers do not turn fully off, making this approach suffer from static power consumption due to the short-circuit currents and reduced noise margins. The standard pMOS transistor pull-up in the active feedback of an inverter reduces the static power consumption but degrades the switching time and/or dynamic power consumption. We propose to use capacitive boosting to increase the gate voltage of the pass transistors, thus driving the multiplexer output to the full high voltage level at a faster rate than the pMOS pull-up can alone. This way, the signal transitions are accelerated and the short-circuit current of downstream buffers are cut off. The simulations carried out with Cadence indicate a reduction of at least 10% in propagation delay for the proposed circuit versus the standard one across 180nm, 130nm, 90nm, and 65nm technologies.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128426549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An Optimized FPGA Implementation of the Modified Space Vector Modulation Algorithm for AC Drives Control 改进空间矢量调制算法在交流驱动器控制中的FPGA优化实现
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.77
B. Alecsa, A. Onea
{"title":"An Optimized FPGA Implementation of the Modified Space Vector Modulation Algorithm for AC Drives Control","authors":"B. Alecsa, A. Onea","doi":"10.1109/FPL.2011.77","DOIUrl":"https://doi.org/10.1109/FPL.2011.77","url":null,"abstract":"This paper presents an optimized FPGA implementation of the 5 step modified space vector modulation algorithm. The algorithm is modeled in Matlab Simulink using System Generator software from Xilinx. After validation through simulation, the algorithm is translated into a synchronous hardware automaton and then implemented in a low cost Spartan-3E FPGA device. Design performance in terms of occupied area and achieved speed is presented and compared to other existing implementations. The algorithm is used in AC drives control, and is especially useful due to minimized switching losses and short execution time. Also, its feature of using only one of the zero space vectors proves advantageous when using a low cost current measurement scheme based on voltage drop over low side shunt resistors. Experimental results verify the correct system functioning and validate the design method.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129420854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Mechanisms and Architecture for the Dynamic Reconfiguration of an Advanced Wireless Sensor Node 一种高级无线传感器节点动态重构的机制和体系结构
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.78
F. Philipp, M. Glesner
{"title":"Mechanisms and Architecture for the Dynamic Reconfiguration of an Advanced Wireless Sensor Node","authors":"F. Philipp, M. Glesner","doi":"10.1109/FPL.2011.78","DOIUrl":"https://doi.org/10.1109/FPL.2011.78","url":null,"abstract":"A dynamically reconfigurable architecture tailored for low power wireless sensor networks is introduced in this work. Using resource sharing and frequent reconfiguration, the power consumption of the hardware is kept low while data processing is still efficient. Remote reconfiguration becomes also possible with very low overhead.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130592677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Scalable FRM-SSA SoC Design for the Simulation of Networks with Thousands of Biochemical Reactions in Real Time 实时模拟数千种生化反应网络的可扩展FRM-SSA SoC设计
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.90
O. Hazapis, E. Manolakos
{"title":"Scalable FRM-SSA SoC Design for the Simulation of Networks with Thousands of Biochemical Reactions in Real Time","authors":"O. Hazapis, E. Manolakos","doi":"10.1109/FPL.2011.90","DOIUrl":"https://doi.org/10.1109/FPL.2011.90","url":null,"abstract":"Simulation of biomolecular networks with thousands of reactions is becoming essential for systems biology. We are presenting the design of a scalable System on Chip parallel architecture that implements Gillespie's First Reaction Method in reconfigurable FPGA hardware. Our SoC architecture can deliver performance (Mega-Reactions/sec) and throughput (M-Reaction cycles/sec) that is increasing linearly with the number of processors when simulating large biomolecular networks with up to m = 4096 reactions using a moderate size FPGA. We have synthesized and verified various SoC instances with up to N=8 Processing Elements for Xilinx Virtex 5 and Altera Cyclone III FPGAs, reaching clock frequencies up to 180 MHz and delivering simulation performance that is more than 2 order of magnitude higher than that of Intel Core 2 and i7 CPUs running at frequencies above 2GHz.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"804 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113999163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures 动态可重构体系结构中故障避免实现可靠性增强的意义
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.108
Hiroaki Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye
{"title":"Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures","authors":"Hiroaki Konoura, Y. Mitsuyama, M. Hashimoto, T. Onoye","doi":"10.1109/FPL.2011.108","DOIUrl":"https://doi.org/10.1109/FPL.2011.108","url":null,"abstract":"Fault avoidance methods on dynamically reconfigurable devices have been proposed to extend device life-time, while their quantitative comparison has not been sufficiently presented. This paper shows results of quantitative life-time evaluation by simulating fault avoidance procedures of representative five methods under the same conditions of wear-out scenario, application and device architecture. Experimental results reveal 1) MTTF is highly correlated with the number of avoided faults, 2) there is the efficiency difference of spare usage in five fault avoidance methods, and 3) spares should be prevented from wear-out not to spoil life-time enhancement.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130129698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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