2011 21st International Conference on Field Programmable Logic and Applications最新文献_第2页

Implementing Stream-Processing Applications on FPGAs: A DSL-Based Approach fpga上实现流处理应用:一种基于dsl的方法

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.32

J. Sérot, F. Berry, Sameer Ahmed

引用次数: 17

Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign FPGA-PCB协同设计的同时约束引脚分配和逃逸路由

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.86

Seong-I Lei, Wai-Kei Mak

引用次数: 5

Real-Time Evaluation of Remote Sensing Data on Board of Satellites 星载遥感数据的实时评估

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.79

K. Schwenk, K. Goetz, M. Schoenermark, F. Huber

引用次数: 1

Exploitation of Parallel Search Space Evaluation with FPGAs in Combinatorial Problems: The Eternity II Case 用fpga开发组合问题中的并行搜索空间评估:永恒II案例

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.53

Pavlos Malakonakis, A. Dollas

引用次数: 4

Scalable Arbiters and Multiplexers for On-FGPA Interconnection Networks On-FGPA互连网络的可扩展仲裁器和多路复用器

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.26

G. Dimitrakopoulos, C. Kachris, E. Kalligeros

引用次数: 10

An Evaluation of Selective Depipelining for FPGA-Based Energy-Reducing Irregular Code Coprocessors 基于fpga的降能不规则码协处理器的选择性去流水线评价

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.16

J. Sampson, Manish Arora, Nathan Goulding, Ganesh Venkatesh, J. Babb, Vikram Bhatt, S. Swanson, M. Taylor

{"title":"An Evaluation of Selective Depipelining for FPGA-Based Energy-Reducing Irregular Code Coprocessors","authors":"J. Sampson, Manish Arora, Nathan Goulding, Ganesh Venkatesh, J. Babb, Vikram Bhatt, S. Swanson, M. Taylor","doi":"10.1109/FPL.2011.16","DOIUrl":"https://doi.org/10.1109/FPL.2011.16","url":null,"abstract":"As the complexity of FPGA-based systems scales, the importance of efficiently handling irregular code increases. Recent work has proposed Irregular Code Energy Reducers (ICERs), a high-level synthesis approach for FPGAs that offers significant energy reduction for irregular code compared to a soft core processor. ICERs target the hot-spots of programs, and are seamlessly connected via a shared L1 cache with a soft processor that executes the cold code. This paper evaluates the application of the selective depipelining (SDP) technique to ICERs, which greatly reduces both the execution time and energy of irregular computations. SDP enables irregular computations to be expressed as large, fast, low-power combinational blocks. SDP maintains high memory bandwidth by scheduling the many potentially dependent memory operations within these blocks onto a high-frequency, highly-multiplexed coherent memory while scheduling combinational operations at a much lower frequency. SDP is a key enabler for improving the execution properties of irregular computations that are difficult to parallelize. We show that applying SDP to ICERs reduces energy-delay by 2.62× relative to ICERs. ICERs with SDP are up to 2.38× faster than a soft core processor and reduce energy consumption by up to 15.83× for a variety of irregular applications.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116164325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs 通过在赛灵思fpga上的交错放置提高sdl设计的安全性

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.100

Rajesh Velegalati, J. Kaps

{"title":"Improving Security of SDDL Designs through Interleaved Placement on Xilinx FPGAs","authors":"Rajesh Velegalati, J. Kaps","doi":"10.1109/FPL.2011.100","DOIUrl":"https://doi.org/10.1109/FPL.2011.100","url":null,"abstract":"Implementations of mathematically secure cryptographic algorithms leak information through side channels during run time. Differential Power Analysis (DPA) attacks exploit power leakage to obtain the secret information. Dynamic and Differential Logic (DDL), one of the popular countermeasures against DPA attacks, tries to achieve constant power consumption thereby decor relating the leakage with the data being processed. Separated Dynamic and Differential Logic (SDDL), a variant of DDL, achieves this goal by duplicating the original design into Direct and Complementary parts which exhibit constant switching activity per clock cycle and have balanced net delays. Traditionally, on Field Programmable Gate Arrays (FPGAs) both parts are placed side-by-side to ensure symmetrical routing. However, due to process variations both parts will have slightly different delays. This limits the effectiveness of SDDL. In this paper we introduce a design flow to achieve interleaved placement of SDDL designs on Xilinx Spartan-3E FPGAs while preserving symmetric routing. We explore several placement configurations with respect to routing and security. The results of our experiments show that a well-balanced placement of SDDL can double the effectiveness of the SDDL countermeasures on FPGAs.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123617612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs IPF:原位x填充以减轻基于ram的fpga中的软错误

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.95

Zhe Feng, Naifeng Jing, Gengsheng Chen, Yu Hu, Lei He

引用次数: 16

An Easily Testable Routing Architecture and Efficient Test Technique 一种易于测试的路由体系结构和有效的测试技术

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.59

Kazuki Inoue, Hiroki Yosho, M. Amagasaki, M. Iida, T. Sueyoshi

引用次数: 10

A Run-Time Adaptive FPGA Architecture for Monte Carlo Simulations 蒙特卡罗仿真的运行时自适应FPGA体系结构

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.30

Xiang Tian, C. Bouganis

{"title":"A Run-Time Adaptive FPGA Architecture for Monte Carlo Simulations","authors":"Xiang Tian, C. Bouganis","doi":"10.1109/FPL.2011.30","DOIUrl":"https://doi.org/10.1109/FPL.2011.30","url":null,"abstract":"Field Programmable Gate Arrays (FPGAs) are now considered to be one of the preferred computing platforms for high performance computing applications, such as Monte Carlo simulations, due to their large computational power and low power consumption. Unlike other state-of-the-art computing platforms, such as General Purpose Processors (GPPs) and General Purpose Graphics Processing Units (GPGPU), FPGAs can moreover exploit the applications' requirements with respect to the employed number representation scheme, with the potential to lead to considerable area savings and throughput increases. This work proposes a novel FPGA based architecture for Monte Carlo simulations that monitors and configures the number representation of the system during run-time in order to accommodate the dynamics of the system under investigation, resulting to a considerable boost on the overall performance of the system compared to a conventional system. In order to evaluate the efficacy of the proposed architecture, the GARCH model from the financial industry is considered as a case study. The results demonstrate that an average of ~1.35x throughput per resource unit improvement is achieved compared to conventional parallel arithmetic implementation.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127023400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11