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2011 21st International Conference on Field Programmable Logic and Applications最新文献

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20Gbps C-Based Complex Event Processing 20Gbps基于c的复杂事件处理
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.27
Hiroaki Inoue, Takashi Takenaka, M. Motomura
{"title":"20Gbps C-Based Complex Event Processing","authors":"Hiroaki Inoue, Takashi Takenaka, M. Motomura","doi":"10.1109/FPL.2011.27","DOIUrl":"https://doi.org/10.1109/FPL.2011.27","url":null,"abstract":"This paper presents the world's fastest complex event processing system, designed to process a large number of events on FPGAs. Unlike conventional SQL-based approaches, our approach features logic automation constructed with a new C-based event language that supports regular expressions on the basis of C functions, so that a wide variety of event-processing applications can be efficiently mapped to FPGAs. Evaluations on an FPGA-based NIC show that we have achieved 20Gbps event processing performance in a financial trading application with only a small logic increase, 2.7%.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122633120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
ERDB: An Embedded Routing Database for Reconfigurable Systems ERDB:可重构系统的嵌入式路由数据库
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.43
Krzysztof Kepa, F. Morgan, P. Athanas
{"title":"ERDB: An Embedded Routing Database for Reconfigurable Systems","authors":"Krzysztof Kepa, F. Morgan, P. Athanas","doi":"10.1109/FPL.2011.43","DOIUrl":"https://doi.org/10.1109/FPL.2011.43","url":null,"abstract":"This work presents an Embedded Routing Database (ERDB), which contains the complete description of the inter-tile routing shapes available in various Xilinx FPGA tiles, and the mapping of Programmable Interconnection Point (PIP) bits within the FPGA configuration bit stream. ERDB provides the RC system with knowledge of its own architecture and facilitates RC systems in implementing autonomic (self-managing and adaptive) computing. ERDB also protects the integrity of the RC system and supports design Intellectual Property (IP) protection. The paper describes the automated generation of a size-optimised ERDB (3.7 MB memory footprint for the Virtex-5 LX50T device) and its application within the Secure Reconfiguration Controller (SeReCon), as a minimised FPGA fabric description for on-line verification of IP core's integrity during partial reconfiguration. Results demonstrate the feasibility and accuracy of the SeReCon/ERDB-based design (IP core) routing verification that, when applied to an example IP block, detects >99% of the configured PIPs.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134184733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Compact CLEFIA Implementation on FPGAS 紧凑的CLEFIA fpga实现
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.101
Paulo Proenca, R. Chaves
{"title":"Compact CLEFIA Implementation on FPGAS","authors":"Paulo Proenca, R. Chaves","doi":"10.1109/FPL.2011.101","DOIUrl":"https://doi.org/10.1109/FPL.2011.101","url":null,"abstract":"In this paper two compact hardware structures for the computation of the CLEFIA encryption algorithm are presented. One structure based on the existing state of the art and a novel structure with a more compact organization. This paper shows that, with the use of the existing embedded FPGA components and a careful scheduling, throughputs above 1Gbit/s can be achieved with a resource usage as low as 86 LUTs and 3 BRAMs on a VIRTEX 5 FPGA. Implementation results suggest that a LUT reduction up to 67% can be achieved at a performance cost of 17% on a VIRTEX 4 FPGA, resulting in Throughput/Slice efficiency gains up to 2.5 times, when compared with the related state of the art.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132208932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Revisiting the Newton-Raphson Iterative Method for Decimal Division 重述Newton-Raphson迭代法的十进制除法
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.33
M. Véstias, H. Neto
{"title":"Revisiting the Newton-Raphson Iterative Method for Decimal Division","authors":"M. Véstias, H. Neto","doi":"10.1109/FPL.2011.33","DOIUrl":"https://doi.org/10.1109/FPL.2011.33","url":null,"abstract":"In this paper, we propose an iterative decimal divider. The divider uses the Newton-Raphson iterative method with an initial approximation calculated with a minimax polynomial and is able to use binary multipliers. The proposed circuits were implemented in an FPGA and compared with alternative state-of-the-art solutions. The results indicate that the proposed divider is very competitive in terms of area and latency and better in terms of throughput when compared to decimal dividers based on digit-recurrence algorithms.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132272685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Dependable Optically Reconfigurable Gate Array with a Phase-Modulation Type Holographic Memory 具有相位调制型全息存储器的可靠光学可重构门阵列
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.17
Takahiro Watanabe, Minoru Watanabe
{"title":"Dependable Optically Reconfigurable Gate Array with a Phase-Modulation Type Holographic Memory","authors":"Takahiro Watanabe, Minoru Watanabe","doi":"10.1109/FPL.2011.17","DOIUrl":"https://doi.org/10.1109/FPL.2011.17","url":null,"abstract":"Optically reconfigurable gate arrays (ORGAs) have been developed as a type of multi-context field programmable gate array. An ORGA's programmable gate array can be reconfigured at nanosecond-order, with more than 100 reconfiguration contexts. In addition to that beneficial feature, since ORGAs can be reconfigured with invalid configuration data that have been damaged by high-energy charged particles in a radiation-rich space environment, ORGAs are suitable for space applications. The robust capability of ORGAs with an amplitude modulation type holographic memory has already been demonstrated, but an ORGA with a phase-modulation type holographic memory that can achieve more robust capability has never been reported. Therefore, this paper presents a proposal of a new dependable ORGA architecture based on a phase-modulation type of holographic memory. In addition, this paper describes experimental clarification through a demonstration that the dependable ORGA is more robust than conventional ORGAs with an amplitude modulation type holographic memory.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114732554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
FPGA Acceleration of the Phylogenetic Parsimony Kernel? 系统演化简约核的FPGA加速?
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.83
Nikolaos S. Alachiotis, A. Stamatakis
{"title":"FPGA Acceleration of the Phylogenetic Parsimony Kernel?","authors":"Nikolaos S. Alachiotis, A. Stamatakis","doi":"10.1109/FPL.2011.83","DOIUrl":"https://doi.org/10.1109/FPL.2011.83","url":null,"abstract":"The phylogenetic parsimony function is a popular, discrete criterion for reconstructing evolutionary trees based on molecular sequence data. Parsimony strives to find the phylogenetic tree that explains the evolutionary history of organisms by the least number of mutations. Because parsimony is a discrete function, it should fit well to FPGAs. We present a versatile FPGA implementation of the parsimony function and compare its performance to a highly optimized SSE3- and AVX-vectorized software implementation. We find that, because of a particular constellation in our lab, the speedups that can be achieved by using an FPGA, are substantially less impressive, than usually reported in papers on FPGA acceleration of bioinformatics kernels. We conclude that, a competitive spirit between SW and HW application developers can contribute toward obtaining more objective performance comparisons.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121736620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Embedded Systems Start-Up under Timing Constraints on Modern FPGAs 现代fpga在时间约束下的嵌入式系统启动
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.28
Joachim Meyer, Juanjo Noguera, M. Hübner, Rodney Stewart, J. Becker
{"title":"Embedded Systems Start-Up under Timing Constraints on Modern FPGAs","authors":"Joachim Meyer, Juanjo Noguera, M. Hübner, Rodney Stewart, J. Becker","doi":"10.1109/FPL.2011.28","DOIUrl":"https://doi.org/10.1109/FPL.2011.28","url":null,"abstract":"In this paper we present novel techniques, methods and tool flows that enable embedded systems implemented on FPGAs to start-up under tight timing constraints (i.e., hard deadlines). Meeting the application deadline is achieved by exploiting the FPGA programmability in order to implement a two-stage system start-up approach, as well as a suitable memory hierarchy. This reduces the FPGA configuration time as well as the startup time of the embedded software. Thereby the start-up time for timing-critical parts of a design neither dependent on the complexity nor on the start-up time of the complete system. An automotive case study is used to demonstrate the feasibility and quantify the benefits of the proposed approach.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123383506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Speculative Debug Insertion for FPGAs fpga的推测调试插入
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.103
Eddie Hung, S. Wilton
{"title":"Speculative Debug Insertion for FPGAs","authors":"Eddie Hung, S. Wilton","doi":"10.1109/FPL.2011.103","DOIUrl":"https://doi.org/10.1109/FPL.2011.103","url":null,"abstract":"FPGA prototypes have become an increasingly important part of the overall integrated circuit design and verification flow, providing the ability to test an integrated circuit running at (near) speed with realistic inputs and outputs. When unexpected behaviour is observed in the prototype, it is necessary to determine the source of this behaviour, this usually requires observing signals that are internal to one of the devices in the prototype. Tools currently exist to enable FPGAs to be instrumented, but these are normally used in a reactive manner, that is, instrumentation is only added after incorrect behaviour has been observed. In this paper, we propose speculative debug insertion, in which a tool automatically predicts what signals will be useful during debug, and instruments the design during the first compilation. If done correctly, this can significantly accelerate the debug process, especially for large prototypes containing many FPGAs. However, it is important that this does not negatively affect the performance, capacity, power, or compilation time. We show that speculative debug insertion is possible, and experimentally evaluate the limits to speculative insertion.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126996953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA 探索Gabor滤波器在FPGA上的视觉皮层建模实现
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.63
Yong Cheol Peter Cho, Sungmin Bae, Yong Jin, K. Irick, N. Vijaykrishnan
{"title":"Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA","authors":"Yong Cheol Peter Cho, Sungmin Bae, Yong Jin, K. Irick, N. Vijaykrishnan","doi":"10.1109/FPL.2011.63","DOIUrl":"https://doi.org/10.1109/FPL.2011.63","url":null,"abstract":"Gabor filters are widely used to model the behavior of the V1 stage of the primary visual cortex of mammalian vision systems. Acceleration of this filter is critical for various real-time vision applications. In this work, we explore a variety of design options for the Gabor filter to tradeoff resource utilization, performance and accuracy. Our results indicate that our optimizations enable a variety of design options to meet a wide range of application constraints.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"16 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120822575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
FPGA-Specific Arithmetic Optimizations of Short-Latency Adders 短延迟加法器的fpga特定算法优化
2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.49
Hong Diep Nguyen, B. Pasca, Thomas B. Preußer
{"title":"FPGA-Specific Arithmetic Optimizations of Short-Latency Adders","authors":"Hong Diep Nguyen, B. Pasca, Thomas B. Preußer","doi":"10.1109/FPL.2011.49","DOIUrl":"https://doi.org/10.1109/FPL.2011.49","url":null,"abstract":"Integer addition is a pervasive operation in FPGA designs. The need for fast wide adders grows with the demand for large precisions as, for example, required for the implementation of IEEE-754 quadruple precision and elliptic-curve cryptography. The FPGA realization of fast and compact binary adders relies on hardware carry chains. These provide a natural implementation environment for the ripple-carry addition (RCA) scheme. As its latency grows linearly with operand width, wide additions call for acceleration, which is quite reasonably achieved by addition schemes built from parallel RCA blocks. This study presents FPGA-specific arithmetic optimizations for the mapping of carry-select and carry-increment adders targeting the hardware carry chains of modern FPGAs. Different trade-offs between latency and area are explored. The proposed architectures can be successfully used in the context of latency-critical systems or as attractive alternatives to deeply pipelined RCA schemes.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"2 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132998997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
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