2011 21st International Conference on Field Programmable Logic and Applications最新文献_第10页

Remote FPGA Lab with Interactive Control and Visualisation Interface 具有交互式控制和可视化界面的远程FPGA实验室

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.98

F. Morgan, Seamus Cawley, F. Callaly, Shane Agnew, P. Rocke, M. O’halloran, Nina Drozd, Krzysztof Kepa, Brian McGinley

引用次数: 22

A Radiation Hard Lut Block with Auto-Scrubbing 具有自动擦洗功能的防辐射硬路块

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.87

Kashfia Haque, P. Beckett

引用次数: 0

Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs H.264/AVC-SVC视频编解码器中块化滤波的运行时可扩展架构

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.72

A. Otero, E. D. L. Torre, T. Riesgo, T. Cervero, S. López, G. Callicó, R. Sarmiento

引用次数: 9

Generic Low-Latency NoC Router Architecture for FPGA Computing Systems FPGA计算系统的通用低延迟NoC路由器架构

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.25

Ye Lu, J. McCanny, S. Sezer

{"title":"Generic Low-Latency NoC Router Architecture for FPGA Computing Systems","authors":"Ye Lu, J. McCanny, S. Sezer","doi":"10.1109/FPL.2011.25","DOIUrl":"https://doi.org/10.1109/FPL.2011.25","url":null,"abstract":"A novel cost-effective and low-latency wormhole router for packet-switched NoC designs, tailored for FPGA, is presented. This has been designed to be scalable at system level to fully exploit the characteristics and constraints of FPGA based systems, rather than custom ASIC technology. A key feature is that it achieves a low packet propagation latency of only two cycles per hop including both router pipeline delay and link traversal delay - a significant enhancement over existing FPGA designs - whilst being very competitive in terms of performance and hardware complexity. It can also be configured in various network topologies including 1-D, 2-D, and 3-D. Detailed design-space exploration has been carried for a range of scaling parameters, with the results of various design trade-offs being presented and discussed. By taking advantage of abundant build-in reconfigurable logic and routing resources, we have been able to create a new scalable on-chip FPGA based router that exhibits high dimensionality and connectivity. The architecture proposed can be easily migrated across many FPGA families to provide flexible, robust and cost-effective NoC solutions suitable for the implementation of high-performance FPGA computing systems.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129003589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 35

Compact Hardware Architecture for Hummingbird Cryptographic Algorithm 蜂鸟密码算法的紧凑硬件架构

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.73

Ismail San, Nuray At

引用次数: 11

Leros: A Tiny Microcontroller for FPGAs 用于fpga的微型微控制器

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-05 DOI: 10.1109/FPL.2011.13

Martin Schoeberl

引用次数: 22

FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Activities 神经种群活动广义Laguerre-Volterra MIMO模型的FPGA结构

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-01 DOI: 10.1109/FPL.2011.19

Will X. Y. Li, Rosa H. M. Chan, Wei Zhang, C. Yu, R. Cheung, D. Song, T. Berger

引用次数: 2

Acceleration of Multi-agent Simulation on FPGAs fpga上多智能体仿真的加速

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-01 DOI: 10.1109/FPL.2011.92

Lintao Cui, Jing Chen, Yu Hu, Jinjun Xiong, Zhe Feng, Lei He

引用次数: 7

Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms 基于sram的FPGA体系结构和综合算法的定量SEU故障评估

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-09-01 DOI: 10.1109/FPL.2011.57

Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Shi-Jie Wen, R. Wong, Lei He

{"title":"Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms","authors":"Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Shi-Jie Wen, R. Wong, Lei He","doi":"10.1109/FPL.2011.57","DOIUrl":"https://doi.org/10.1109/FPL.2011.57","url":null,"abstract":"This paper studies the SEU (Single Event Upset) fault for SRAM-based FPGAs. Considering detailed fault behavior on various circuit elements in a post-layout FPGA application, we develop a simulation-based SEU evaluation tool that quantifies fault contribution for each configuration bit. Using this tool and MCNC benchmark circuits, we study the fault characteristics of FPGA circuits and architectures. We show that interconnects not only contribute to the lion share of functional failures, but also have higher failure rate per configuration bit than LUTs. Particularly, multiplexers in local interconnects have the highest failure rate per bit. We find that tuning LUT and cluster sizes helps to reduce the rate (up to 38% in our experiments). In addition, we evaluate two recent fault mitigation algorithms IPD and IPF, which reduce LUT faults by an average of 74% and 15% respectively. But when interconnects are taken into account, the reduction via IPD which considers only LUT faults is merely 6% on chip level. Yet the reduction via IPF which implicitly considers interconnect faults is still around 15%. Therefore, synthesis algorithm should be evaluated with interconnect faults and future algorithms should be developed with consideration of interconnect faults explicitly.","PeriodicalId":311066,"journal":{"name":"2011 21st International Conference on Field Programmable Logic and Applications","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120850286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry 基于结构对称的FPGA时序良率改进研究

2011 21st International Conference on Field Programmable Logic and Applications Pub Date : 2011-02-27 DOI: 10.1145/1950413.1950467

Haile Yu, Qiang Xu, P. Leong

引用次数: 2