Capacitive Boosting for FPGA Interconnection Networks

Abstract

FPGA interconnection network is implemented using nMOS pass transistor multiplexers. Since the threshold voltage drop across an nMOS device degrades the high logic value, the pMOS transistors of the downstream buffers do not turn fully off, making this approach suffer from static power consumption due to the short-circuit currents and reduced noise margins. The standard pMOS transistor pull-up in the active feedback of an inverter reduces the static power consumption but degrades the switching time and/or dynamic power consumption. We propose to use capacitive boosting to increase the gate voltage of the pass transistors, thus driving the multiplexer output to the full high voltage level at a faster rate than the pMOS pull-up can alone. This way, the signal transitions are accelerated and the short-circuit current of downstream buffers are cut off. The simulations carried out with Cadence indicate a reduction of at least 10% in propagation delay for the proposed circuit versus the standard one across 180nm, 130nm, 90nm, and 65nm technologies.