A Radix Tree Router for Scalable FPGA Networks

Abstract

Many FPGA based Network-on-Chip (NoC) and directly connected clusters use routers implemented in the FPGA fabric. Existing projects have optimized the routers for low resource utilization, low latency, and high bandwidth, often at the cost of programmability and manageability. Developers using the existing FPGA networks often have no way to specify a source or destination of a message except by using the physical locations of the nodes in the network. This low level of abstraction limits developer productivity and the ability of the network to adapt to changing conditions. We present an FPGA network that resolves these issues by allowing the developer to use familiar 32-bit addresses similar to an IP address and a router that uses a software managed routing table. The implementation presented here demonstrates similar resource utilization and bandwidth with a minimal increase in latency when compared to existing FPGA router implementations.