2016 74th Annual Device Research Conference (DRC)最新文献_第2页

Electrical performance enhancement of 20 nm scale graphene nanoribbon field-effect transistors with dipolar molecules 用偶极分子增强20纳米尺度石墨烯纳米带场效应晶体管的电性能

2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7548454

Seohee Kim, Saungeun Park, D. Akinwande, A. Dodabalapur

{"title":"Electrical performance enhancement of 20 nm scale graphene nanoribbon field-effect transistors with dipolar molecules","authors":"Seohee Kim, Saungeun Park, D. Akinwande, A. Dodabalapur","doi":"10.1109/DRC.2016.7548454","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548454","url":null,"abstract":"Graphene Nanoribbons (GNR) are been being investigated as they possess a bandgap in contrast to graphene sheets which have zero bandgap [1, 2]. Therefore, GNR might be more suitable as a channel material in field-effect transistors (FETs) which requires a high on/off ratio. The other electrical properties of GNR FETs apart from on/off ratio, however, are not as good as those of corresponding graphene sheet FETs. Most GNR FETs have a larger hysteresis, a lower mobility and a larger Dirac voltage than those of graphene sheet FETs. The critical factor that results in degraded performance of GNR FET is edge defects, since GNR due to their geometry have a larger number of edges per active channel width. Moreover, edges of patterned GNR from chemical vapor deposition (CVD) grown graphene do not have a perfect chirality and inevitably have more broken bonds. Thus defect passivation or amelioration assumes considerable importance if the excellent potential of GNR as a semiconducting material is to be realized. In this abstract we report the effect of polar vapors on the electrical characteristics of GNR FET, which is fabricated via patterning from CVD grown graphene monolayer sheet. Our goal is to use these as model studies in designing suitable cap layers that both protect the nanoribbons from the ambient and favorably influence, to a considerable degree, their electrical properties.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117182205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Fermi level tunability of a novel 2D crystal: Tin Diselenide (SnSe2) 一种新型二维晶体:二硒化锡(SnSe2)的费米能级可调性

2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7548473

Mingda Li, S. Xiao, R. Yan, S. Vishwanath, S. Fullerton‐Shirey, D. Jena, H. Xing

{"title":"Fermi level tunability of a novel 2D crystal: Tin Diselenide (SnSe2)","authors":"Mingda Li, S. Xiao, R. Yan, S. Vishwanath, S. Fullerton‐Shirey, D. Jena, H. Xing","doi":"10.1109/DRC.2016.7548473","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548473","url":null,"abstract":"Tin Diselenide (SnSe2) is a two-dimensional layered crystal commonly found in octahedral coordination (1T phase). It has been reported to have a high electron affinity of around 5.1 eV and a bandgap of 1 eV [1-2], which can form staggered band alignment with tungsten diselenide (WSe2) in Thin-TFETs [3]. However, its lack of gate modulation remains a mystery [4]. In this work, we investigate the Fermi level tunability of SnSe2 by counter doping using a polymer electrolyte, PEO:CsClO4. This counter doping technique increases the on/off ratio of SnSe2 field effect transistor (FET) from 2 times to 50 times, a record high value. Meanwhile, a device model of SnSe2 FET with ion doping and subgap density of states (DOS) has been proposed to fit the experimental data. The extracted effective number of acceptor-like subgap states is as high as 4.16 × 1019 cm-3 (in comparison with near 5 × 1017 cm-3 extracted for amorphous thin-film transistors [5]). This can explain the weak Fermi level tunability of SnSe2 and direct future material development towards TFETs.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126092513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Phase-change materials for reconfigurable RF applications 可重构射频应用的相变材料

2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7548404

J. Moon, H. Seo, K. Son, Jack A. Crowell, D. Le, D. Zehnder

引用次数: 1

Model-based high-precision tuning of NOR flash memory cells for analog computing applications 基于模型的模拟计算应用的NOR闪存单元高精度调谐

2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7548449

F. M. Bayat, X. Guo, M. Klachko, N. Do, K. Likharev, D. Strukov

引用次数: 25

Deep ultraviolet enhanced silicon carbide avalanche photodiodes 深紫外增强碳化硅雪崩光电二极管

2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7548420

A. Sampath, Y. Chen, J. Smith, S. Kelley, J. Schuster, G. Garret, H. Shen, J. Campbell, M. Wraback, M. Reed

引用次数: 0

Exploring channel doping designs for high-performance tunneling FETs 探索高性能隧道场效应管的沟道掺杂设计

2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7548456

Jun Z. Huang, P. Long, M. Povolotskyi, M. Rodwell, Gerhard Klimeck

{"title":"Exploring channel doping designs for high-performance tunneling FETs","authors":"Jun Z. Huang, P. Long, M. Povolotskyi, M. Rodwell, Gerhard Klimeck","doi":"10.1109/DRC.2016.7548456","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548456","url":null,"abstract":"Future high-performance low-power integrated circuits require compact logic devices with both steep subthreshold swing (SS) and large drive current (ION). Tunneling field-effect transistors (TFETs) can meet the first requirement but their ION is severely limited either by the low source-channel tunneling probability or by the high source-to-drain tunneling leakage. One of the methods that can be employed to boost ION is doping engineering. In particular (1)lowering the drain doping density elongates the drain depletion region and thus suppresses the leakage leading to improved SS (and ION). This scheme, however, is not scalable as a long drain length is needed to reach charge neutrality; (2) embedding an opposite N+ doping layer next to the P+ source, i.e., the source-pocket (SP) design, or inserting a δ doping layer, can enhance the electric field at the source-channel tunnel junction and improve ION. It can be shown that the improvement increases as the pocket doping density (Np) increases, but in practice doping density has an upper limit. In this paper, we show that, (1) embedding a P+ drain pocket can also improve the SS (and ION) and it is more scalable than lowering the drain doping; (2) by resorting to P+ channel, we can further improve ION of the SP design without having to increase Np.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132489578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Finding a proper place for photons in the world full of electrons and their spins 在充满电子和自旋的世界里为光子找到合适的位置

2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7548516

J. Khurgin

{"title":"Finding a proper place for photons in the world full of electrons and their spins","authors":"J. Khurgin","doi":"10.1109/DRC.2016.7548516","DOIUrl":"https://doi.org/10.1109/DRC.2016.7548516","url":null,"abstract":"Summary form only given. It has been half a century since the photons have been portended to supplant electrons in information transmission, storage, and processing. While spectacular successes have been achieved in optical communications and these advances are slowly working their way into the chip-scale optical interconnects, optical memories have not displaced magnetic storage and are now losing ground to the all-electronic flash memories, and, in information processing the competitive all-optical switching schemes have never materialized. The fundamental reason for these facts is crystal clear - unlike electrons, photons are bosons that do not have charge and are not subjected to Pauli principle, and hence they are ideally suited for the unhindered propagation over spectacular distances while requiring quite an effort in order to be switched. We confirm this intuitive understanding by comparing switching powers, speeds and noise of electronic and photonic devices, such as modulators, all optical switches and buffers. At the same time we show that in terms of loss and bandwidth photons are unmatchable for information transmission even over the shortest of distances and cannot be replaced by any known entity, including currently popular plasmons. With electrons and photons having their clearly defined niches the main challenge lays in developing means for seamless connectivity between electronics and photonics.","PeriodicalId":310524,"journal":{"name":"2016 74th Annual Device Research Conference (DRC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134236620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Transistor innovation in the 21st century — A lesson in serendipity 21世纪的晶体管创新——意外发现的教训

2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7548288

S. Datta

引用次数: 1

Introducing the spiked p-n junction for tunnel devices and current gain 介绍了隧道器件的尖刺pn结和电流增益

2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7548415

S. Bader, D. Jena

引用次数: 0

An energy efficient memory device based on fixed magnetic skyrmions switched with an electric field 一种以电场开关的固定磁存储器为基础的节能存储器

2016 74th Annual Device Research Conference (DRC) Pub Date : 2016-06-19 DOI: 10.1109/DRC.2016.7548418

Dhritiman Bhattacharya, M. Al-Rashid, J. Atulasimha

引用次数: 0