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2014 IEEE International Electron Devices Meeting最新文献

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First demonstration of high-Ge-content strained-Si1−xGex (x=0.5) on insulator PMOS FinFETs with high hole mobility and aggressively scaled fin dimensions and gate lengths for high-performance applications 首次在绝缘体PMOS finfet上展示了高锗含量应变si1−xGex (x=0.5)，具有高空穴迁移率和可扩展的翅片尺寸和栅极长度，可用于高性能应用
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7047061
P. Hashemi, K. Balakrishnan, S. Engelmann, J. Ott, A. Khakifirooz, A. Baraskar, M. Hopstaken, J. Newbury, Kevin K. H. Chan, E. Leobandung, R. Mo, Dae-gyu Park
{"title":"First demonstration of high-Ge-content strained-Si1−xGex (x=0.5) on insulator PMOS FinFETs with high hole mobility and aggressively scaled fin dimensions and gate lengths for high-performance applications","authors":"P. Hashemi, K. Balakrishnan, S. Engelmann, J. Ott, A. Khakifirooz, A. Baraskar, M. Hopstaken, J. Newbury, Kevin K. H. Chan, E. Leobandung, R. Mo, Dae-gyu Park","doi":"10.1109/IEDM.2014.7047061","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047061","url":null,"abstract":"For the first time, we report fabrication and characterization of high-performance s-Si<sub>1-x</sub>Ge<sub>x</sub>-OI (x~0.5) pMOS FinFETs with aggressively scaled dimensions. We demonstrate realization of s-SiGe fins with W<sub>FIN</sub> =3.3nm and devices with L<sub>G</sub>=16nm, in a CMOS compatible process. Using a Si-cap-free passivation, we report SS=68mV/dec and μ<sub>eff</sub>=390±12 cm<sup>2</sup>/Vs at N<sub>inv</sub>=10<sup>13</sup>cm<sup>-2</sup>, outperforming the state-of-the-art relaxed Ge FinFETs. We also report the highest performance reported to date among sub-20nm-L<sub>G</sub> pMOS FinFETs at V<sub>DD</sub>=0.5V. In addition, hole transport as well as electrostatics, performance and leakage characteristics of SGOI FinFETs for various dimensions are comprehensively studied in this work.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"126 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132846244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
A manufacturable interposer MIM decoupling capacitor with robust thin high-K dielectric for heterogeneous 3D IC CoWoS wafer level system integration 一种可制造的具有坚固薄高k介电体的中间体MIM去耦电容器，用于异构3D IC coos晶圆级系统集成
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7047119
W. Liao, C. H. Chang, S. W. Huang, T. H. Liu, H. P. Hu, H. L. Lin, C. Tsai, C. Tsai, H. Chu, C. Pai, W. Chiang, S. Hou, S. Jeng, Doug C. H. Yu
{"title":"A manufacturable interposer MIM decoupling capacitor with robust thin high-K dielectric for heterogeneous 3D IC CoWoS wafer level system integration","authors":"W. Liao, C. H. Chang, S. W. Huang, T. H. Liu, H. P. Hu, H. L. Lin, C. Tsai, C. Tsai, H. Chu, C. Pai, W. Chiang, S. Hou, S. Jeng, Doug C. H. Yu","doi":"10.1109/IEDM.2014.7047119","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047119","url":null,"abstract":"A reliability proven high-K (HK) metal-insulator-metal (MiM) structure has been verified within the silicon interposer in a chip-on-wafer-on-substrate (CoWoS) packaging for heterogeneous system-level decoupling application. The HK dielectric has an equivalent oxide thickness (EOT) of 20Å, intrinsic TDDB lifetime of 322 years at an operation voltage (V<sub>cc</sub>) of 1.8V, and a leakage current (I<sub>LK</sub>) below 1 fA/μm<sup>2</sup> under +/-2V bias at 125°C. The measured unit area capacitance density for the single, 2- and 3-in-series Si-interposer HK-MiM combination is 17.2, 4.3 and 1.9 fF/μm<sup>2</sup>, respectively, with their corresponding I<sub>LK</sub> below 0.48, 0.19 and 0.09 fAmp/μm<sup>2</sup>. Process reliability related defect density (D<sub>0</sub>) of the interposer HK-MiM is as low as 0.095% cm<sup>-2</sup> as judged by a 10 years lifetime breakdown voltage (V<sub>bd</sub>) criterion at V<sub>cc</sub>=3.2V. This low D<sub>0</sub> ensures the Si-interposer HK-MiM to be used in a large area over 1056 cm<sup>2</sup> within the Si interposer. Moreover, the V<sub>bd</sub> tolerance of the HK-MiM can be drastically enhanced to be 9.75 and 14.25V, respectively, by 2- and 3-in-series HK-MiM configuration connection. At the package level during all steps of CoWoS processing, no distinguishable process induced damage (PID) and performance degradation (Cap., I<sub>LK</sub> & V<sub>bd</sub> tailing) were detected. Therefore, this high capacitance, low leakage, large area and reliability-proven Si-interposer decoupling capacitor (DeCAP) within CoWoS greatly enhances the merit of using Si-interposer HK-MiM capacitors for multi-chip system-level integration.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132853076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Impact of low-frequency noise on read distributions of resistive switching memory (RRAM) 低频噪声对电阻式开关存储器(RRAM)读分布的影响
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7047051
S. Ambrogio, S. Balatti, V. McCaffrey, D. Wang, D. Ielmini
{"title":"Impact of low-frequency noise on read distributions of resistive switching memory (RRAM)","authors":"S. Ambrogio, S. Balatti, V. McCaffrey, D. Wang, D. Ielmini","doi":"10.1109/IEDM.2014.7047051","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047051","url":null,"abstract":"Resistive switching memory (RRAM) is one of the most promising emerging device technology for future storage and computing memories. As other emerging memories based on materials storage at the nanoscale, RRAM is affected by switching and read fluctuations. We addressed current fluctuation in RRAM at both cell and array levels. First, we present an analytical model for 1/f and random telegraph noise (RTN) in single (intrinsic) cells, allowing to predict time-dependent broadening of read current Iread distributions. Then we address tail cells with statistically-high noise in large arrays, revealing time-decaying random walk (RW) and intermittent RTN phenomena for the first time. A statistical noise model capable of explaining the current distribution broadening in RRAM arrays is finally developed and discussed.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"573 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132518626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
High performance metal oxide TFT and its applications for thin film electronics 高性能金属氧化物TFT及其在薄膜电子中的应用
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7047112
Gang Yu, C. Shieh, J. Musolf, F. Foong, Tianzi Xiao, Guangming Wang, K. Ottosson
{"title":"High performance metal oxide TFT and its applications for thin film electronics","authors":"Gang Yu, C. Shieh, J. Musolf, F. Foong, Tianzi Xiao, Guangming Wang, K. Ottosson","doi":"10.1109/IEDM.2014.7047112","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047112","url":null,"abstract":"Recent progress on metal-oxide TFT with mobility and stability as good as LTPS-TFT and with uniformity and off current as good as pristine a-Si TFT are presented. Their applications for high pixel density displays and image arrays are discussed with emphasis on pixel and peripheral circuits with analog functions.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123850167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High-precision wafer-level Cu-Cu bonding for 3DICs 用于3dic的高精度晶圆级Cu-Cu键合
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7047118
M. Okada, Isao Sugaya, Hajime Mitsuishi, Hidehiro Maeda, T. Shimoda, S. Izumi, Hosei Nakahira, K. Okamoto
{"title":"High-precision wafer-level Cu-Cu bonding for 3DICs","authors":"M. Okada, Isao Sugaya, Hajime Mitsuishi, Hidehiro Maeda, T. Shimoda, S. Izumi, Hosei Nakahira, K. Okamoto","doi":"10.1109/IEDM.2014.7047118","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047118","url":null,"abstract":"A high-precision Cu-Cu bonding system for three-dimensional integrated circuits (3DICs) fabrication adopting a new precision alignment methodology is proposed. A new pressure profile control system is applied in the thermocompression bonding process. Experimental results show that the alignment capability is 250 nm or better, with similar overlay accuracy (|average| + 3σ) for permanent bonding. These developments are expected to contribute to the fabrication of future 3DICs.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128613670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
New Framework for the random charging/discharging of oxide traps in HfO2 gate dielectric: ab-initio simulation and experimental evidence HfO2栅极介质中氧化物阱随机充放电的新框架:ab-initio模拟和实验证据
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7047096
Jingwei Ji, Y. Qiu, Shaofeng Guo, Runsheng Wang, P. Ren, P. Hao, Ru Huang
{"title":"New Framework for the random charging/discharging of oxide traps in HfO2 gate dielectric: ab-initio simulation and experimental evidence","authors":"Jingwei Ji, Y. Qiu, Shaofeng Guo, Runsheng Wang, P. Ren, P. Hao, Ru Huang","doi":"10.1109/IEDM.2014.7047096","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047096","url":null,"abstract":"A new framework for first-principle simulation on random charging/discharging of individual oxide traps is established and adopted for detailed studies on HfO2 high-k gate dielectrics for the first time. The proposed framework provides an effective solution to the challenges in conventional multi-phonon simulation methodology, and successfully explains various experimental results in HfO2 devices. 1-DOV defect, instead of traditionally assumed SOV, is found to be the crime oxide trap in HfO2. And the anomalous RTN observations strongly support the high-order four-state model, which can be well explained by the two metastable states found in the 2-DOV defect. The framework is helpful for the fundamental understanding of RTN and NBTI reliability.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128750228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
High Ion/Ioff Ge-source ultrathin body strained-SOI tunnel FETs 高离子/ off锗源超薄体应变soi隧道场效应管
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7047043
Minsoo Kim, Y. Wakabayashi, R. Nakane, M. Yokoyama, M. Takenaka, S. Takagi
{"title":"High Ion/Ioff Ge-source ultrathin body strained-SOI tunnel FETs","authors":"Minsoo Kim, Y. Wakabayashi, R. Nakane, M. Yokoyama, M. Takenaka, S. Takagi","doi":"10.1109/IEDM.2014.7047043","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047043","url":null,"abstract":"High performance operation of Ge-source/strained-Si-channel hetero-junction tunnel FETs is demonstrated. It is found that tensile strain in Si-channels can enhance the tunneling current because of the reduced effective energy bandgap, Eg.eff. Nitrogen heat-treatment can improve the gate-to-channel MIS interface which causes SS improvement. The fabricated Ge/sSOI(1.1 %) tunnel FETs show high Ion/Ioff ratio over 107 and steep minimum SS of 28 mV/dec. Back biasing effects are also investigated and the Ion and average SS are improved by positive back biasing.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129252920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 59
Challenges of analog and I/O scaling in 10nm SoC technology and beyond 在10nm及以后的SoC技术中模拟和I/O扩展的挑战
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7047076
A. Wei, J. Singh, G. Bouche, M. Zaleski, R. Augur, B. Senapati, Jason Eugene Stephens, I. Lin, M. Rashed, L. Yuan, J. Kye, Y. Woo, J. Zeng, H. Levinson, A. Wehbi, P. Hang, V. Ton-That, V. Kanagala, D. Yu, D. Blackwell, A. Beece, S. Gao, S. Thangaraju, R. Alapati, S. Samavedam
{"title":"Challenges of analog and I/O scaling in 10nm SoC technology and beyond","authors":"A. Wei, J. Singh, G. Bouche, M. Zaleski, R. Augur, B. Senapati, Jason Eugene Stephens, I. Lin, M. Rashed, L. Yuan, J. Kye, Y. Woo, J. Zeng, H. Levinson, A. Wehbi, P. Hang, V. Ton-That, V. Kanagala, D. Yu, D. Blackwell, A. Beece, S. Gao, S. Thangaraju, R. Alapati, S. Samavedam","doi":"10.1109/IEDM.2014.7047076","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047076","url":null,"abstract":"Continuous process-level and system-level innovation has driven Moore's Law scaling for the last fifty years, and will continue to do so in the next decades. In the last two decades, there has been an acceleration of new materials and devices into semiconductor manufacturing, such as low-k, strained Si, high-k, and FinFET, in order to continue process and cost scaling. At the same time, ever increasing component integration on SoCs has further driven cost scaling, allowing the current mobile era to take shape. In the next decade, the focus of SoC innovation will be on patterning and low-resistance materials on the process side, and multi-die package integration on the system side.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115853120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Bio-integrated systems with stretchable designs for skin-mounted wearable health monitoring 具有可拉伸设计的生物集成系统，用于皮肤安装的可穿戴健康监测
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7047151
M. Raj, P. Wei, Shyamal Patel, Xianyan Wang, Bryan McGrane, Lauren E. Klinker, P. DePetrillo, R. Ghaffari
{"title":"Bio-integrated systems with stretchable designs for skin-mounted wearable health monitoring","authors":"M. Raj, P. Wei, Shyamal Patel, Xianyan Wang, Bryan McGrane, Lauren E. Klinker, P. DePetrillo, R. Ghaffari","doi":"10.1109/IEDM.2014.7047151","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047151","url":null,"abstract":"We present ultrathin, flexible and stretchable epidermal health monitoring devices that contain physiological sensors, an analog front end processor, a core microprocessor, flash memory module, rechargeable battery, and a wireless communication (Bluetooth low energy) module. The system is mechanically matched to the Young's modulus of human skin and designed to record heart rate, electromyography signals, activity, respiration and sleep quality to facilitate continuous (electro-)physiological data recording outside of the hospital setting.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117104945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Progress in ultrahigh-voltage SiC devices for future power infrastructure 未来电力基础设施的超高压SiC器件的进展
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7046967
T. Kimoto, J. Suda, Y. Yonezawa, K. Asano, K. Fukuda, H. Okumura
{"title":"Progress in ultrahigh-voltage SiC devices for future power infrastructure","authors":"T. Kimoto, J. Suda, Y. Yonezawa, K. Asano, K. Fukuda, H. Okumura","doi":"10.1109/IEDM.2014.7046967","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7046967","url":null,"abstract":"UHV (> 15 kV) SiC PiN diodes and IGBTs with improved on-state performance are presented. Through enhancement of carrier lifetime and optimization of junction termination, a breakdown voltage over 26.9 kV and a differential on-resistance of 9.7 mΩcm2 were achieved for PiN diodes. Flip-type n-channel IGBTs with a chip size of 8 mm × 8 mm exhibited a breakdown voltage over 16 kV, and 6.5 kV - 60 A switching at 250°C was demonstrated.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114540953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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