2014 IEEE International Electron Devices Meeting最新文献

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New understanding of state-loss in complex RTN: Statistical experimental study, trap interaction models, and impact on circuits 复杂RTN中状态损失的新认识:统计实验研究,陷阱相互作用模型,以及对电路的影响
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7047169
Jibin Zou, Runsheng Wang, Shaofeng Guo, Mulong Luo, Zhuoqing Yu, Xiaobo Jiang, P. Ren, Jianping Wang, Jinhua Liu, Jingang Wu, W. Wong, Shaofeng Yu, Hanming Wu, Shiuh-Wuu Lee, Yangyuan Wang, Ru Huang
{"title":"New understanding of state-loss in complex RTN: Statistical experimental study, trap interaction models, and impact on circuits","authors":"Jibin Zou, Runsheng Wang, Shaofeng Guo, Mulong Luo, Zhuoqing Yu, Xiaobo Jiang, P. Ren, Jianping Wang, Jinhua Liu, Jingang Wu, W. Wong, Shaofeng Yu, Hanming Wu, Shiuh-Wuu Lee, Yangyuan Wang, Ru Huang","doi":"10.1109/IEDM.2014.7047169","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047169","url":null,"abstract":"In this paper, the statistical characteristics of complex RTN (both DC and AC) are experimentally studied for the first time, rather than limited case-by-case studies. It is found that, over 50% of RTN-states predicted by conventional theory are lost in actual complex RTN statistics. Based on the mechanisms of non-negligible trap interactions, new models are proposed, which successfully interpret this state-loss behavior, as well as the different complex RTN characteristics in SiON and high-κ devices. The circuit-level study also indicates that, predicting circuit stability would have large errors if not taking into account the trap interactions and RTN state-loss. The results are helpful for the robust circuit design against RTN.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122510365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Fast visible-light phototransistor using CVD-synthesized large-area bilayer WSe2 利用cvd合成大面积双层WSe2的快速可见光光电晶体管
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7046992
Pang-Shiuan Liu, Chang-Hsiao Chen, W. Hsu, Chih-Pin Lin, Tzu-Ping Lin, Li-Jen Chi, Chao-Yuan Chang, Shih-Chieh Wu, Wen‐Hao Chang, Lain‐Jong Li, T. Hou
{"title":"Fast visible-light phototransistor using CVD-synthesized large-area bilayer WSe2","authors":"Pang-Shiuan Liu, Chang-Hsiao Chen, W. Hsu, Chih-Pin Lin, Tzu-Ping Lin, Li-Jen Chi, Chao-Yuan Chang, Shih-Chieh Wu, Wen‐Hao Chang, Lain‐Jong Li, T. Hou","doi":"10.1109/IEDM.2014.7046992","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7046992","url":null,"abstract":"P-channel transition metal dichalcogenide ultrathin-body phototransistor (UTB-PT) with a response time as fast as 100 μs has been demonstrated for the first time using the CVD-synthesized large-area bilayer WSe2. Because of its excellent compatibility with mass production, the application of WSe2 UTB-PT for high-speed proximity interactive display has been proposed.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122605499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Direct observation of self-heating in III–V gate-all-around nanowire MOSFETs III-V栅极全能纳米线mosfet自热的直接观察
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7047088
S. Shin, M. Masuduzzaman, M. A. Wahab, K. Maize, J. Gu, M. Si, A. Shakouri, P. Ye, M. Alam
{"title":"Direct observation of self-heating in III–V gate-all-around nanowire MOSFETs","authors":"S. Shin, M. Masuduzzaman, M. A. Wahab, K. Maize, J. Gu, M. Si, A. Shakouri, P. Ye, M. Alam","doi":"10.1109/IEDM.2014.7047088","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047088","url":null,"abstract":"Gate-all-around MOSFETs use multiple nanowires to achieve target ION, along with excellent 3D electrostatic control of the channel. Although self-heating effect (SHE) has been a persistent concern, the existing characterization methods, based on indirect measure of mobility and specialized test structures, do not offer adequate spatio-temporal resolution. In this paper, we develop an ultra-fast, high resolution thermo-reflectance (TR) imaging technique to (i) directly observe the increase in local surface temperature of the GAA-FET with different number of nanowires (NWs), (ii) characterize/interpret the time constants of heating and cooling through high resolution transient measurements, (iii) identify critical paths for heat dissipation, and (iv) detect in-situ time-dependent breakdown of individual NW. Our approach also allows indirect imaging of quasi-ballistic transport and corresponding drain/source asymmetry of self-heating. Combined with the complementary approaches that probe the internal temperature of the NW, the TR-images offer a high resolution map of self-heating in the surround-gate devices with unprecedented precision, necessary for validation of electro-thermal models and optimization of devices and circuits.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122906816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
Controlling oxygen vacancies in doped oxide based CBRAM for improved memory performances 控制掺杂氧化物基CBRAM的氧空位以改善记忆性能
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7046993
G. Molas, E. Vianello, F. Dahmani, M. Barci, P. Blaise, J. Guy, A. Toffoli, M. Bernard, A. Roule, F. Pierre, C. Licitra, B. De Salvo, L. Perniola
{"title":"Controlling oxygen vacancies in doped oxide based CBRAM for improved memory performances","authors":"G. Molas, E. Vianello, F. Dahmani, M. Barci, P. Blaise, J. Guy, A. Toffoli, M. Bernard, A. Roule, F. Pierre, C. Licitra, B. De Salvo, L. Perniola","doi":"10.1109/IEDM.2014.7046993","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7046993","url":null,"abstract":"In this paper the concept hybrid CBRAM assisted by oxygen vacancies is presented for the 1<;sup>st<;/sup> time. Doping the resistive layer of oxide/Cu based CBRAM with <; dopant species and concentrations is proposed in order to improve the memory performances. By means of experimental characterizations, numerical model and atomistic calculations, we demonstrate that increasing the doping content ease the filament formation by facilitating the Cu injection in the resistive layer. The proper choice of the doping element and concentration allows to significantly reduce the forming voltage (up to a forming free behavior), or alternatively to increase the memory window of 3 decades, with no forming voltage increase and retention degradation (stable behavior at 200°C, 260°C soldering sustained).","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131600620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Atomically thin graphene plane electrode for 3D RRAM 用于3D RRAM的原子薄石墨烯平面电极
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7046988
Joon Sohn, Seunghyun Lee, Zizhen Jiang, Hong-Yu Chen, H. Wong
{"title":"Atomically thin graphene plane electrode for 3D RRAM","authors":"Joon Sohn, Seunghyun Lee, Zizhen Jiang, Hong-Yu Chen, H. Wong","doi":"10.1109/IEDM.2014.7046988","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7046988","url":null,"abstract":"3Å thick graphene edge was employed in the bit-cost scalable vertical RRAM structure to drastically reduce the total stack height to a single atomic layer. Two-layer 3D-stacked HfOx RRAM with graphene planar electrode (G-RRAM) is demonstrated in a 3D cross-point architecture with the edge of the graphene plane electrode serving as the bottom electrode of the RRAM. Exceptional memory window (>80×), low reset current (~20 μA), and suitable set/reset voltages (2 to 4 V) were achieved. Large memory window and low SET compliance ensures low reset current and low power consumption. Resistance components were separately measured to verify the role of graphene/oxide interface and the graphene sheet resistance. This work is a significant step toward extreme vertical scaling of 3D vertical stacked memory structures.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128106659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Poly pitch and standard cell co-optimization below 28nm 聚节距与标准电池在28nm以下协同优化
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7047041
M. Frederick
{"title":"Poly pitch and standard cell co-optimization below 28nm","authors":"M. Frederick","doi":"10.1109/IEDM.2014.7047041","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047041","url":null,"abstract":"In sub-28nm technologies, the scaling of poly pitch while beneficial for area typically has a negative impact on device performance. The primary limitation is the non-scaling physical channel length and the device level parasitic impact on effective device performance. Therefore, it is important to scale the poly pitch in line with the maximum routable pin density supported by a process to achieve optimal power, performance, and cost (area).","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133437814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Ultra low contact resistivity (< 1×10−8 Ω-cm2) to In0.53Ga0.47As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III–V fin TLM structure fabricated with III–V on Si substrates 超低接触电阻率(< 1×10−8 Ω-cm2)至In0.53Ga0.47As鳍侧壁(110)/(100)表面:采用VLSI加工的III-V鳍TLM结构,在Si衬底上由III-V制成
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7047155
Rinus Lee, Y. Ohsawa, C. Huffman, Y. Trickett, G. Nakamura, C. Hatem, K. V. Rao, F. Khaja, R. Lin, K. Matthews, K. Dunn, A. Jensen, T. Karpowicz, P. Nielsen, E. Stinzianni, A. Cordes, P. Hung, D. Kim, R. Hill, W. Loh, C. Hobbs
{"title":"Ultra low contact resistivity (< 1×10−8 Ω-cm2) to In0.53Ga0.47As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III–V fin TLM structure fabricated with III–V on Si substrates","authors":"Rinus Lee, Y. Ohsawa, C. Huffman, Y. Trickett, G. Nakamura, C. Hatem, K. V. Rao, F. Khaja, R. Lin, K. Matthews, K. Dunn, A. Jensen, T. Karpowicz, P. Nielsen, E. Stinzianni, A. Cordes, P. Hung, D. Kim, R. Hill, W. Loh, C. Hobbs","doi":"10.1109/IEDM.2014.7047155","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047155","url":null,"abstract":"We report a record low contact resistivity of sub-1.0×10<sup>-8</sup> Ω.cm<sup>2</sup> realized on n<sup>+</sup> In<sub>0.53</sub>Ga<sub>0.47</sub>As fin sidewall surfaces. This is achieved with VLSI processed fin TLM structures on wafer scale III-V on Si substrates. A novel low-damage III-V fin etch was developed and fins down to 35 nm were fabricated. A surface treatment to smoothen the fin sidewall surfaces was proposed, which reduced sidewall surface roughness variation by 90%. Additionally, we show for the first time that implant temperature could be used to eliminate implant damage in III-V fins. This increased activation efficiency (+3.6×) and reduced sheet resistance (-60%).","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"55 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131791618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
An integrated tunable laser using nano-silicon-photonic circuits 采用纳米硅光子电路的集成可调谐激光器
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7047060
M. Ren, H. Cai, J. Tao, Y. D. Gu, K. Radhakrishnan, Z. Yang, D. Kwong, A. Liu
{"title":"An integrated tunable laser using nano-silicon-photonic circuits","authors":"M. Ren, H. Cai, J. Tao, Y. D. Gu, K. Radhakrishnan, Z. Yang, D. Kwong, A. Liu","doi":"10.1109/IEDM.2014.7047060","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047060","url":null,"abstract":"This paper reports an integrated tunable laser using nano-silicon-photonic circuits. In particular, all the necessary optical functions in an external cavity laser system, including the beam transmission, coupling, filtering and reflection, are realized using waveguide-based circuits. The high light-confinement capability of the nano-silicon waveguides avoids high optical loss in free-space as suffered in the conventional Microelectromechanical Systems (MEMS) tunable lasers, and thus guarantees superior performance. The proposed laser demonstrates large tuning range (45 nm), pure single-mode properties (45 dB side-mode-suppression ratio (SMSR)), and relatively high output power (~1 mW).","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132118190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Imaging with organic and hybrid photodetectors 用有机和混合光电探测器成像
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7047024
S. Tedde, Patric Buchele, R. Fischer, F. Steinbacher, O. Schmidt
{"title":"Imaging with organic and hybrid photodetectors","authors":"S. Tedde, Patric Buchele, R. Fischer, F. Steinbacher, O. Schmidt","doi":"10.1109/IEDM.2014.7047024","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047024","url":null,"abstract":"Organic semiconductors provide exiting new opportunities for the realization of flat panel image sensors as they can be processed from the solution phase on large areas at low cost. In particular the high charge separation efficiency obtained in a bulk heterojunction (BHJ) enables the realization of organic photodiodes (OPDs). The spectral sensitivity of OPDs can be tailored to cover wavelengths ranging from the visible to the near infrared region. These sensitivities match perfectly to a variety of X-ray scintillators enabling a further improvement in the sensitivity range. In combination with an amorphous silicon (a-Si) thin film transistor (TFT) backplane technology, visible, near infrared (NIR) and X-ray image sensors have been realized. Thin film OPDs have been used in combination with a cesium iodide (CsI) scintillator in a traditional stacked geometry, proofing state-of-the art performance. Even more, it is possible to blend X-ray absorbing particles directly into the organic semiconductor thereby enabling quasi-direct X-ray converters with the promise to achieve a modulation transfer function (MTF) that is as high as in direct converting materials such as amorphous Selenium.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122975022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Pulsed cycling operation and endurance failure of metal-oxide resistive (RRAM) 金属氧化物电阻(RRAM)的脉冲循环运行与耐久性失效
2014 IEEE International Electron Devices Meeting Pub Date : 2014-12-01 DOI: 10.1109/IEDM.2014.7047050
S. Balatti, S. Ambrogio, Z.-Q Wang, S. Sills, A. Calderoni, N. Ramaswamy, D. Ielmini
{"title":"Pulsed cycling operation and endurance failure of metal-oxide resistive (RRAM)","authors":"S. Balatti, S. Ambrogio, Z.-Q Wang, S. Sills, A. Calderoni, N. Ramaswamy, D. Ielmini","doi":"10.1109/IEDM.2014.7047050","DOIUrl":"https://doi.org/10.1109/IEDM.2014.7047050","url":null,"abstract":"Oxide-based resistive memory (RRAM) is under scrutiny for possible use for non-volatile storage and storage-class memory (SCM) complementing DRAM and SRAM. For SCM applications, set/reset times, variability and endurance are key concerns, which must be carefully understood to explore potential applications of RRAM. To that purpose we studied pulsed operation and endurance of oxide RRAM. We show that (i) resistance window (RW) is controlled by the negative voltage Vstop applied during reset, (ii) failure at high Vstop is due to negative set, causing filament overgrowth and RW collapse and (iii) endurance is independent of the pulse-width, which supports an Arrhenius model for endurance failure.","PeriodicalId":309325,"journal":{"name":"2014 IEEE International Electron Devices Meeting","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125053032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
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