Poly pitch and standard cell co-optimization below 28nm

Abstract

In sub-28nm technologies, the scaling of poly pitch while beneficial for area typically has a negative impact on device performance. The primary limitation is the non-scaling physical channel length and the device level parasitic impact on effective device performance. Therefore, it is important to scale the poly pitch in line with the maximum routable pin density supported by a process to achieve optimal power, performance, and cost (area).