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2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)最新文献

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Optimizing of the inkjet printing technique parameters for fabrication of bulk heterojunction organic solar cells 体异质结有机太阳能电池喷墨打印工艺参数的优化
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549447
V. Fauzia, A. Umar, M. Salleh, M. Yahya
{"title":"Optimizing of the inkjet printing technique parameters for fabrication of bulk heterojunction organic solar cells","authors":"V. Fauzia, A. Umar, M. Salleh, M. Yahya","doi":"10.1109/SMELEC.2010.5549447","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549447","url":null,"abstract":"The inkjet printing technique is a promising alternative deposition technique due to its effectiveness in material use and large area coverage. However, the printed film morphology critically depends on the droplets characteristics. This paper reports the optimizing of several key printing parameters, such as pulse voltages, drop spacing and waveform setting for obtaining the high quality droplets and printed film for organic solar cell application. The organic printed film is an active layer of bulk heterojunction solar cells that is composed of blended poly (3-octylthiophene)(P3OT) and (6,6)-phenyl C71 butyric acid methyl ester (PCBM). The film was printed on ITO coated glass substrate. The absorption and morphology study of the printed film and the performance of photovoltaic devices characterized by current-voltage measurement in the dark and under illumination are reported. The dependence of setting of printing parameters on the droplets and film quality will be discussed.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129268924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The effect of gate oxide thickness and drain bias on NBTI degradation in 45nm PMOS 栅极氧化物厚度和漏极偏压对45nm PMOS中NBTI降解的影响
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549558
S. Hatta, N. Soin, J. F. Zhang
{"title":"The effect of gate oxide thickness and drain bias on NBTI degradation in 45nm PMOS","authors":"S. Hatta, N. Soin, J. F. Zhang","doi":"10.1109/SMELEC.2010.5549558","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549558","url":null,"abstract":"This paper presents the effects of gate oxide scaling and drain bias variation on the Negative Bias Temperature Instabilities (NBTI) of a 45nm PMOSFET. The gate oxide thickness parameter is varied in this work at values of 1.8nm, 2nm and 3nm. The drain bias of the PMOS is also varied, at values 50mV and 1.2V, in order to observe its effect on the NBTI of the PMOS. The effects on the fundamental device parameters namely the interface trap concentration, threshold voltage and drain current had been studied utilizing the technology CAD (TCAD) Sentaurus Synopsys simulator. At decreasing gate oxide thickness, the PMOS transistor presents a higher interface trap concentration but exhibits improvement in the threshold voltage shift and less degradation in the drain current, when a high stress temperature and large negative bias are applied. In addition to that, the stressed transistor would exhibit significant current degradation at a higher drain bias.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129497625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A proposed low power voltage multiplier for passive UHF RFID transponder 一种用于无源超高频RFID应答器的低功率电压乘法器
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549377
P. Fahsyar, N. Soin
{"title":"A proposed low power voltage multiplier for passive UHF RFID transponder","authors":"P. Fahsyar, N. Soin","doi":"10.1109/SMELEC.2010.5549377","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549377","url":null,"abstract":"The design of a low power voltage multiplier for passive UHF RFID transponder which compatible with CMOS process and can be applied to the surroundings in where the distance from the reader changes greatly is presented in this paper. The functioning principle of N-stage voltage multiplier is introduced in this paper. With the intention of maximizing the operating range of RFID tag, low power design techniques are necessary. Therefore, the key design parameters optimization is discussed. The transistor size (W/L) and number of stages (N) are varied in order to attain the great value of output voltage and power efficiency. This proposed design is implemented in 0.18µm process. The calculated and simulated result shows that the four-stage voltage multiplier can work at frequency 900MHz by using 8µm transistor size and the power efficiency is 34% with output voltage 1.2V.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124787429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Characterization of fabrication process noises for 32nm NMOS devices 32nm NMOS器件制造过程噪声表征
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549581
H. A. Elgomati, B. Majlis, I. Ahmad, T. Ziad
{"title":"Characterization of fabrication process noises for 32nm NMOS devices","authors":"H. A. Elgomati, B. Majlis, I. Ahmad, T. Ziad","doi":"10.1109/SMELEC.2010.5549581","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549581","url":null,"abstract":"This paper describes the effect of fabrication process noises to Sub-nanometer devices, which in this case a 32nm NMOS transistor. This experiment a part of a full Taguchi Method analysis to obtain an optimum fabrication recipe for the said transistor. The two noises introduced in the fabrication is ±1°C variation in sacrificial oxide layer growth by diffusion temperature and also silicide compress annealing temperature. In this project, a working 32 NMOS transistor fabrication is used. By increasing the sacrificial oxide layer diffusion temperature from 900°C to 901°C, the reference 32nm NMOS transistor threshold voltage (VTH) jumps from 0.1181V to 0.1394V, while leakage current drops from 0.111mA/um to 0.109 mA/um. By decreasing the silicide compress temperature from 910°C to 909°C, threshold voltage increase slightly from 0.118053V to 0.118068V, This shows a very different in magnitude of effect from same degree of noise introduce to the fabrication process.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121845680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of cantilever shape on the power output of a piezoelectric bimorph generator 悬臂梁形状对压电双晶片发电机输出功率的影响
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549360
Akeel Shebeeb, H. Salleh
{"title":"Effect of cantilever shape on the power output of a piezoelectric bimorph generator","authors":"Akeel Shebeeb, H. Salleh","doi":"10.1109/SMELEC.2010.5549360","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549360","url":null,"abstract":"This paper discusses the effect of the cantilever shape of piezoelectric bimorph bender on the power output. ANSYS® program was used to study the distribution of stress strain in each model design and MATLAB® program was used to simulate the effect of each variable on the output power. Triangular, rectangular and trapezoidal cantilevers were chosen with wide range of frequencies between (50Hz – 150 Hz) with the same input excitation conditions and same volumetric size, to analyze the effect of each design in the power. The result shows that maximum stress-strain value can be produced in the triangular shape with equal distribution on all the surface area. The analytical simulation showed that the maximum value of power of 5 mW at 85 Hz was produced by the triangular cantilever beam. Thus, triangular shape can produce maximum power comparing with the others.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126840747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Strain cancellation by indium incorporation for the calibration of nitrogen fractions in GaAsN 加铟对GaAsN中氮组分校正的应变抵消
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549495
H. Hashim, B. Usher
{"title":"Strain cancellation by indium incorporation for the calibration of nitrogen fractions in GaAsN","authors":"H. Hashim, B. Usher","doi":"10.1109/SMELEC.2010.5549495","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549495","url":null,"abstract":"This paper reports a study of strain cancellation by adding indium to GaAs<inf>1−y</inf>N<inf>y</inf> epitaxial layers as a method of calibrating the nitrogen fraction y. The aim was to determine the In fraction x in an In<inf>x</inf>Ga<inf>1−x</inf>As<inf>1−y</inf>N<inf>y</inf> epitaxial layer which exactly cancels the strain present in a GaAs<inf>1−y</inf>N<inf>y</inf> layer with the same nitrogen content when grown on a GaAs substrate. This is an alternative to asserting nitrogen fractions in GaAs<inf>1−y</inf>N<inf>y</inf> layers on the basis of x-ray measurements, when the values and linearity of lattice and elastic constants with nitrogen composition y has not been established. The GaAs<inf>1−y</inf>N<inf>y</inf> and In<inf>x</inf>Ga<inf>1−x</inf>As<inf>1−y</inf>N<inf>y</inf> layers were grown on GaAs (001) substrates using molecular beam epitaxy with an electron cyclotron resonance nitrogen plasma source. Layers have been assessed by high-resolution x-ray diffraction to determine the relationship between the lattice constant of the GaAs<inf>1−y</inf>N<inf>y</inf> layer and the fraction x of In required to exactly cancel the strain.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127229243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An extension of input sample acceptance for SELA MC600 micro-cleaving tool 扩展了SELA MC600微切割工具的输入样品接受度
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549535
H. Ahmataku, K. Kipli
{"title":"An extension of input sample acceptance for SELA MC600 micro-cleaving tool","authors":"H. Ahmataku, K. Kipli","doi":"10.1109/SMELEC.2010.5549535","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549535","url":null,"abstract":"Minimum input sample size and thickness for SELA MC600, a micro-cleaving tool, is 9 × 6 mm and 0.6 mm respectively. The machine will reject sample which is smaller or thinner than this acceptance value. But, in semiconductor Failure Analysis (FA) laboratories, it is inevitable to face such small and thin sample, for instance, a die from backgrinded wafer. Therefore, a technique named Dual-Edged Cleaving (DEC) is invented to circumvent this restriction.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127948801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design analysis of single layer coupled coils 单层耦合线圈的设计分析
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549375
J. Yunas, N. Sulaiman, A. Bahadorimehr, B. Majlis
{"title":"Design analysis of single layer coupled coils","authors":"J. Yunas, N. Sulaiman, A. Bahadorimehr, B. Majlis","doi":"10.1109/SMELEC.2010.5549375","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549375","url":null,"abstract":"This paper presents an analysis on the design of coupled coil. The coil platform that has been developed is a single layer coil structure on the planar surface of the substrate. the structure offers an integrated solution for customizable application due to its compact and small size. The design of the spiral coil has been analysed using field solver analysis ASITIC. As a demonstration of the usefulness of such analysis, a coupled coil is fabricated on a glass substrate and measured at frequency range between 50 MHz and 800 MHz. A coupling factor of about 0.7 and self inductance of 12.7 nH were achieved which show a good agreement with the simulation.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129158754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reduced parasitic capacitances analysis of nanoscale vertical MOSFET 纳米级垂直MOSFET的减小寄生电容分析
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549485
I. Saad, M. Riyadi, Zul Atfyi F. M. N., R. Ismail
{"title":"Reduced parasitic capacitances analysis of nanoscale vertical MOSFET","authors":"I. Saad, M. Riyadi, Zul Atfyi F. M. N., R. Ismail","doi":"10.1109/SMELEC.2010.5549485","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549485","url":null,"abstract":"Quantitative comparison analysis was made between standard vertical MOSFET, vertical MOSFET with FILOX (Fillet Local Oxidation) and vertical MOSFET that combine ORI (Oblique Rotating Implantation) and FILOX technology. Due to a very thin gate oxide separated the gate track and source/drain electrode in standard vertical MOSFET, tremendous increase effects of gate-to-drain and gate-to-source parasitic capacitances was observed. The FILOX device was found to have a lower gate-to-source capacitance compared to FILOX + ORI device due to titled implants used in ORI for self-aligned S/D region formation and SCE control. Thus, thicker oxide on the top and bottom of silicon pillar or so-called FILOX structure has significantly reduce the intrinsic gate capacitance. However, with the addition of titled implants in FILOX + ORI device, the gate-to-drain capacitance has been significantly reduced while has a small difference (10 – 15%) of reducing gate-to-source capacitance as compared to FILOX device. Therefore, the addition of ORI method can suppress the effect of intrinsic gate capacitances and deliberately control the SCE with the self-aligned S/D region onto silicon pillar as scaling the device into nanometer realm.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"7 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131148402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Linearity effect in formation of four wave mixing capitalising FBGs characteristics 利用fbg特性形成四波混频的线性效应
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549353
M. N. Abdullah, A. Ehsan, M. N. Z. Abidin, A. Abidin
{"title":"Linearity effect in formation of four wave mixing capitalising FBGs characteristics","authors":"M. N. Abdullah, A. Ehsan, M. N. Z. Abidin, A. Abidin","doi":"10.1109/SMELEC.2010.5549353","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549353","url":null,"abstract":"An experiment to determine the correlation of power in effect of four wave mixing (FWM) by obtaining the linearity of power towards FWM formation. A fibre ring laser configuration consists of amplifier set up and arrangement of FBGs is described. Encouraging results obtained from the set up proves the relations of power variable perspective which associated through FWM generation.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128618237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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