发布求助
文献互助 智能选刊 最新文献

2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)最新文献

筛选
英文 中文
Regional clock gate splitting algorithm for clock tree synthesis 时钟树合成的区域时钟门分割算法
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549384
Siong Kiong Teng, N. Soin
{"title":"Regional clock gate splitting algorithm for clock tree synthesis","authors":"Siong Kiong Teng, N. Soin","doi":"10.1109/SMELEC.2010.5549384","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549384","url":null,"abstract":"In this paper, the new clock distribution design flow and algorithm of clock gate splitting to improve the clock gate's enable signal timing violations had been presented. The clock gate components in a clock tree are exposed to setup timing violations due to the nature that the clock gates skew is normally big as they are located at the beginning of the clock tree. The effective splitting of the clock gate to the lower level of the clock tree will improve the clock gate skew and thus improve the setup margin.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134639871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Characterization of fabrication process noises for 32nm NMOS devices 32nm NMOS器件制造过程噪声表征
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549581
H. A. Elgomati, B. Majlis, I. Ahmad, T. Ziad
{"title":"Characterization of fabrication process noises for 32nm NMOS devices","authors":"H. A. Elgomati, B. Majlis, I. Ahmad, T. Ziad","doi":"10.1109/SMELEC.2010.5549581","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549581","url":null,"abstract":"This paper describes the effect of fabrication process noises to Sub-nanometer devices, which in this case a 32nm NMOS transistor. This experiment a part of a full Taguchi Method analysis to obtain an optimum fabrication recipe for the said transistor. The two noises introduced in the fabrication is ±1°C variation in sacrificial oxide layer growth by diffusion temperature and also silicide compress annealing temperature. In this project, a working 32 NMOS transistor fabrication is used. By increasing the sacrificial oxide layer diffusion temperature from 900°C to 901°C, the reference 32nm NMOS transistor threshold voltage (VTH) jumps from 0.1181V to 0.1394V, while leakage current drops from 0.111mA/um to 0.109 mA/um. By decreasing the silicide compress temperature from 910°C to 909°C, threshold voltage increase slightly from 0.118053V to 0.118068V, This shows a very different in magnitude of effect from same degree of noise introduce to the fabrication process.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121845680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Linearity effect in formation of four wave mixing capitalising FBGs characteristics 利用fbg特性形成四波混频的线性效应
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549353
M. N. Abdullah, A. Ehsan, M. N. Z. Abidin, A. Abidin
{"title":"Linearity effect in formation of four wave mixing capitalising FBGs characteristics","authors":"M. N. Abdullah, A. Ehsan, M. N. Z. Abidin, A. Abidin","doi":"10.1109/SMELEC.2010.5549353","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549353","url":null,"abstract":"An experiment to determine the correlation of power in effect of four wave mixing (FWM) by obtaining the linearity of power towards FWM formation. A fibre ring laser configuration consists of amplifier set up and arrangement of FBGs is described. Encouraging results obtained from the set up proves the relations of power variable perspective which associated through FWM generation.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128618237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Genetic algorithm based extraction method for distributed small-signal model of GaN HEMTs 基于遗传算法的GaN hemt分布式小信号模型提取方法
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549476
Anwar Jarnda
{"title":"Genetic algorithm based extraction method for distributed small-signal model of GaN HEMTs","authors":"Anwar Jarnda","doi":"10.1109/SMELEC.2010.5549476","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549476","url":null,"abstract":"In this paper, an improved small-signal model parameter extraction method, using genetic algorithm (GA), is presented and implemented for GaN HEMT. The GA optimization is used to generate a high quality reliable starting values for the elements of distributed model. This value are then refined using local optimization technique to find optimal value for each model element. The developed extraction method is validated by simulating S-parameter measurements of a 8x125-µm gate width GaN HEMT over a wide bias range.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130026571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Optimizing of the inkjet printing technique parameters for fabrication of bulk heterojunction organic solar cells 体异质结有机太阳能电池喷墨打印工艺参数的优化
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549447
V. Fauzia, A. Umar, M. Salleh, M. Yahya
{"title":"Optimizing of the inkjet printing technique parameters for fabrication of bulk heterojunction organic solar cells","authors":"V. Fauzia, A. Umar, M. Salleh, M. Yahya","doi":"10.1109/SMELEC.2010.5549447","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549447","url":null,"abstract":"The inkjet printing technique is a promising alternative deposition technique due to its effectiveness in material use and large area coverage. However, the printed film morphology critically depends on the droplets characteristics. This paper reports the optimizing of several key printing parameters, such as pulse voltages, drop spacing and waveform setting for obtaining the high quality droplets and printed film for organic solar cell application. The organic printed film is an active layer of bulk heterojunction solar cells that is composed of blended poly (3-octylthiophene)(P3OT) and (6,6)-phenyl C71 butyric acid methyl ester (PCBM). The film was printed on ITO coated glass substrate. The absorption and morphology study of the printed film and the performance of photovoltaic devices characterized by current-voltage measurement in the dark and under illumination are reported. The dependence of setting of printing parameters on the droplets and film quality will be discussed.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129268924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
The effect of gate oxide thickness and drain bias on NBTI degradation in 45nm PMOS 栅极氧化物厚度和漏极偏压对45nm PMOS中NBTI降解的影响
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549558
S. Hatta, N. Soin, J. F. Zhang
{"title":"The effect of gate oxide thickness and drain bias on NBTI degradation in 45nm PMOS","authors":"S. Hatta, N. Soin, J. F. Zhang","doi":"10.1109/SMELEC.2010.5549558","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549558","url":null,"abstract":"This paper presents the effects of gate oxide scaling and drain bias variation on the Negative Bias Temperature Instabilities (NBTI) of a 45nm PMOSFET. The gate oxide thickness parameter is varied in this work at values of 1.8nm, 2nm and 3nm. The drain bias of the PMOS is also varied, at values 50mV and 1.2V, in order to observe its effect on the NBTI of the PMOS. The effects on the fundamental device parameters namely the interface trap concentration, threshold voltage and drain current had been studied utilizing the technology CAD (TCAD) Sentaurus Synopsys simulator. At decreasing gate oxide thickness, the PMOS transistor presents a higher interface trap concentration but exhibits improvement in the threshold voltage shift and less degradation in the drain current, when a high stress temperature and large negative bias are applied. In addition to that, the stressed transistor would exhibit significant current degradation at a higher drain bias.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129497625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Reduced parasitic capacitances analysis of nanoscale vertical MOSFET 纳米级垂直MOSFET的减小寄生电容分析
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549485
I. Saad, M. Riyadi, Zul Atfyi F. M. N., R. Ismail
{"title":"Reduced parasitic capacitances analysis of nanoscale vertical MOSFET","authors":"I. Saad, M. Riyadi, Zul Atfyi F. M. N., R. Ismail","doi":"10.1109/SMELEC.2010.5549485","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549485","url":null,"abstract":"Quantitative comparison analysis was made between standard vertical MOSFET, vertical MOSFET with FILOX (Fillet Local Oxidation) and vertical MOSFET that combine ORI (Oblique Rotating Implantation) and FILOX technology. Due to a very thin gate oxide separated the gate track and source/drain electrode in standard vertical MOSFET, tremendous increase effects of gate-to-drain and gate-to-source parasitic capacitances was observed. The FILOX device was found to have a lower gate-to-source capacitance compared to FILOX + ORI device due to titled implants used in ORI for self-aligned S/D region formation and SCE control. Thus, thicker oxide on the top and bottom of silicon pillar or so-called FILOX structure has significantly reduce the intrinsic gate capacitance. However, with the addition of titled implants in FILOX + ORI device, the gate-to-drain capacitance has been significantly reduced while has a small difference (10 – 15%) of reducing gate-to-source capacitance as compared to FILOX device. Therefore, the addition of ORI method can suppress the effect of intrinsic gate capacitances and deliberately control the SCE with the self-aligned S/D region onto silicon pillar as scaling the device into nanometer realm.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"7 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131148402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An extension of input sample acceptance for SELA MC600 micro-cleaving tool 扩展了SELA MC600微切割工具的输入样品接受度
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549535
H. Ahmataku, K. Kipli
{"title":"An extension of input sample acceptance for SELA MC600 micro-cleaving tool","authors":"H. Ahmataku, K. Kipli","doi":"10.1109/SMELEC.2010.5549535","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549535","url":null,"abstract":"Minimum input sample size and thickness for SELA MC600, a micro-cleaving tool, is 9 × 6 mm and 0.6 mm respectively. The machine will reject sample which is smaller or thinner than this acceptance value. But, in semiconductor Failure Analysis (FA) laboratories, it is inevitable to face such small and thin sample, for instance, a die from backgrinded wafer. Therefore, a technique named Dual-Edged Cleaving (DEC) is invented to circumvent this restriction.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127948801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Strain cancellation by indium incorporation for the calibration of nitrogen fractions in GaAsN 加铟对GaAsN中氮组分校正的应变抵消
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549495
H. Hashim, B. Usher
{"title":"Strain cancellation by indium incorporation for the calibration of nitrogen fractions in GaAsN","authors":"H. Hashim, B. Usher","doi":"10.1109/SMELEC.2010.5549495","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549495","url":null,"abstract":"This paper reports a study of strain cancellation by adding indium to GaAs<inf>1−y</inf>N<inf>y</inf> epitaxial layers as a method of calibrating the nitrogen fraction y. The aim was to determine the In fraction x in an In<inf>x</inf>Ga<inf>1−x</inf>As<inf>1−y</inf>N<inf>y</inf> epitaxial layer which exactly cancels the strain present in a GaAs<inf>1−y</inf>N<inf>y</inf> layer with the same nitrogen content when grown on a GaAs substrate. This is an alternative to asserting nitrogen fractions in GaAs<inf>1−y</inf>N<inf>y</inf> layers on the basis of x-ray measurements, when the values and linearity of lattice and elastic constants with nitrogen composition y has not been established. The GaAs<inf>1−y</inf>N<inf>y</inf> and In<inf>x</inf>Ga<inf>1−x</inf>As<inf>1−y</inf>N<inf>y</inf> layers were grown on GaAs (001) substrates using molecular beam epitaxy with an electron cyclotron resonance nitrogen plasma source. Layers have been assessed by high-resolution x-ray diffraction to determine the relationship between the lattice constant of the GaAs<inf>1−y</inf>N<inf>y</inf> layer and the fraction x of In required to exactly cancel the strain.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127229243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Optimum design of SU-8 based accelerometer with reduced cross axis sensitivity 降低交叉轴灵敏度的SU-8型加速度计优化设计
2010 IEEE International Conference on Semiconductor Electronics (ICSE2010) Pub Date : 2010-06-28 DOI: 10.1109/SMELEC.2010.5549364
P. Ray, V. Rao, P. Apte
{"title":"Optimum design of SU-8 based accelerometer with reduced cross axis sensitivity","authors":"P. Ray, V. Rao, P. Apte","doi":"10.1109/SMELEC.2010.5549364","DOIUrl":"https://doi.org/10.1109/SMELEC.2010.5549364","url":null,"abstract":"The work presented here shows a new design for SU8 based piezoresistive accelerometer, where SU8/carbon black is used as piezoresistors. The accelerometer structure is optimized to generate maximum bending stress at the base of the beams. The structure is inherently temperature insensitive. The design of proof mass is such that the sensitivity to cross axis acceleration is kept within a limit of 4%.","PeriodicalId":308501,"journal":{"name":"2010 IEEE International Conference on Semiconductor Electronics (ICSE2010)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113959429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信