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Proceedings. VLSI and Computer Peripherals. COMPEURO 89最新文献

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Japanese handwriting recognition using AI techniques 使用人工智能技术的日语手写识别
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93393
D. Inman
{"title":"Japanese handwriting recognition using AI techniques","authors":"D. Inman","doi":"10.1109/CMPEUR.1989.93393","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93393","url":null,"abstract":"An online computer system has been developed to recognize handwritten Japanese Hiragana characters. The system requires only detection of pen-up and the velocity of the pen in the two horizontal planes of the paper. No absolute coordinates need be collected. This enables a user to write naturally on paper while recognition takes place, using a biro pen modified with a rubber membrane and three strain gauges. Such tolerance towards the user creates scope for considerable ambiguity, techniques from artificial intelligence, in particular from natural-language processing are used to help with this problem. A grammar is used to describe the target character shapes, and the input stream is classified by parsing. For characters close to the target, the most likely of the hypotheses was correct for over 95% of the characters drawn by three native Japanese. For poorly drawn characters the recognition rate, based upon the most likely hypothesis, drops to around 80%, but the set of hypotheses almost always contains the target character.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128678115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
VLSI architecture for image transformation 用于图像变换的VLSI架构
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93389
H. Cheng, Y.Y. Tang, C. Suen, Q. S. Gao
{"title":"VLSI architecture for image transformation","authors":"H. Cheng, Y.Y. Tang, C. Suen, Q. S. Gao","doi":"10.1109/CMPEUR.1989.93389","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93389","url":null,"abstract":"Several theorems on image transformations are proved, and new algorithms are proposed to perform these functions. These algorithms perform mapping and filling at the same time, while respecting the connectivity of the original image. As a result, the transformations become more consistent and accurate. The essential parallelism in the new algorithms also facilitates their implementation using VLSI architecture, such that the time complexity is the only O(N) compared with O(N/sup 2/) using a uniprocessor, where n is the dimension of the image plane. The new algorithms can handle all kinds of images, including those of long narrow objects which present problems to other algorithms. They also reduce the errors introduced by the order in which rotation and scaling are applied. A series of experiments was conducted to verify the performance of the proposed algorithms. The results indicate that the new algorithms and VLSI architectures can be very useful to image-processing, pattern recognition, and related areas, especially real-time applications.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121038730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Signal processing for high-density digital magnetic recording 高密度数字磁记录的信号处理
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93353
F. Dolivo
{"title":"Signal processing for high-density digital magnetic recording","authors":"F. Dolivo","doi":"10.1109/CMPEUR.1989.93353","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93353","url":null,"abstract":"The signal-processing techniques most often used in digital magnetic recording systems are run-length limited (RLL) coding and peak detection (PD). The application of more advanced methods, such as partial-response (PR) signaling and maximum-likelihood sequence detection (MLSD), allows a further increase in the recording densities and reliability presently achieved. After reviewing RLL coding an PD schemes, recording systems using PR signaling and MLSD (PRML) are described. Viterbi decoding and decision-directed algorithms for automatic gain control and timing recovery are discussed for the two types of PR scheme best suited for magnetic recording, class-IV (PR-IV) and extended class-IV (EPR-IV). Results of a performance study on PD and PRML systems which demonstrate the superiority of the PRML approach are presented. For the two PRML systems considered, sensitivity to various parameters and performance in an off-track situation were investigated. The results shown indicate that the two schemes are equally robust and that PR-IV signaling is superior to EPR-IV in off-track situations. A PRML system based on PR-IV signaling is also simpler to realize.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"373 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122773888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
High speed nonvolatile memories employing ferroelectric technology 采用铁电技术的高速非易失性存储器
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93335
F. Gnadinger
{"title":"High speed nonvolatile memories employing ferroelectric technology","authors":"F. Gnadinger","doi":"10.1109/CMPEUR.1989.93335","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93335","url":null,"abstract":"The problems encountered in early attempts to build a ferroelectric memory are described. A combination of design innovations and process and materials breakthroughs that can overcome these problems is presented. PZT (lead zirconate titanate) is chosen as the basic ferroelectric material and integrated into a standard CMOS process. PZT has a wide temperature range (+350 degrees C Curie temperature), low coercive voltage, high specific polarization charge (10-20 mu C/cm/sup 2/), and good retention and endurance. The lack of a well-defined coercive field was overcome with a DRAM-like circuit architecture, which provides for transistor switches in series, with each ferroelectric element preventing disturb pulses from affecting the unselected cells. As a demonstration vehicle, a fully decoded 256-b nonvolatile ferroelectric random-access memory (FRAM) was developed. The switching speed inherent in the PZT material was found to be on the order of 1 ns. The high switching speed and the high signal charge, which render the technology highly scalable, offer the potential to build nonvolatile semiconductor memories with the speed of static RAMs and the density and cost of dynamic RAMs.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"272 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116576273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Experimenting natural-language dictation with a 20000-word speech recognizer 用2万字语音识别器进行自然语言听写实验
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93377
P. Alto, M. Brandetti, M. Ferretti, G. Maltese, S. Scarci
{"title":"Experimenting natural-language dictation with a 20000-word speech recognizer","authors":"P. Alto, M. Brandetti, M. Ferretti, G. Maltese, S. Scarci","doi":"10.1109/CMPEUR.1989.93377","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93377","url":null,"abstract":"The authors describe a newly developed real-time large-vocabulary speech recognizer for the Italian language and some preliminary experiments on its usage. Some of these experiments are aimed at evaluating voice versus keyboard as a means for entry and editing of texts. The experiments made use of a dictating-machine prototype for the Italian language, which recognizes in real time natural-language sentences built from a 20000-word vocabulary. A voice-activated editor was developed to allow the user to create, revise, file, and print documents. It is found that large-vocabulary speech recognition can offer a very competitive alternative to traditional text entry. It is likely to be well accepted even by users who have a large experience in keyboard text editing. The study has already suggested possible improvements to the man-machine interface of the current speech recognizer.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125923375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Trends in data acquisition for testing in nuclear power stations 核电站测试数据采集的趋势
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93423
J. Mazalerat, J. Favennec
{"title":"Trends in data acquisition for testing in nuclear power stations","authors":"J. Mazalerat, J. Favennec","doi":"10.1109/CMPEUR.1989.93423","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93423","url":null,"abstract":"Electricite de France (EDF), the French electric utility, performs extensive testing on its nuclear power plants for commissioning needs or optimization purposes. The required instrumentation must meet demanding metrological, functional, and technological specifications. Smart sensors are a significant step in instrumentation. They provide higher accuracy of measurement, identification and validation of information, and consistent data. The authors described EDF's strategy for the architecture, power supply, communication, and configuration of smart sensor systems for testing needs. Tests performed on the Saint Alban power plant demonstrate the feasibility of the distributed consumption test-system concept, which allows decentralization of measurement acquisition and estimation of the amount of money saved by reduced wiring.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131493055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Implementation aspects of the pan-European digital mobile radio system 泛欧数字移动无线电系统的实施方面
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93435
P. Vary
{"title":"Implementation aspects of the pan-European digital mobile radio system","authors":"P. Vary","doi":"10.1109/CMPEUR.1989.93435","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93435","url":null,"abstract":"In 1991 a digital mobile radio system, the so-called Group Special Mobile (GSM) system, will be introduced in Europe. The author presents the modulation and coding techniques which have been standardized recently For the GSM. for the baseband processing algorithms of speech coding, channel coding, and adaptive equalization, VLSI requirements are addressed. The new system has been designed for a capacity of about 10 million subscribers in Europe. Hand-held pocket telephones are expected to play a major role. The typical requirements are weight <0.8 kg, volume <900 cm, stand-by operation >24 h, and active operation >1 h. A major problem is the reduction of the power consumption, which requires that certain functions be switched off in the standby mode.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134407168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
E/sup 2/PROM product issues and technology trends E/sup 2/PROM产品问题及技术趋势
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93334
W. Owen, W.E. Tchon
{"title":"E/sup 2/PROM product issues and technology trends","authors":"W. Owen, W.E. Tchon","doi":"10.1109/CMPEUR.1989.93334","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93334","url":null,"abstract":"The E/sup 2/PROM (electrically erasable and programmable read-only memory), the fastest growing new form of solid-state memory, combines nonvolatility and changeability which can be changed by simple logic-level signals, therefore providing in-system change capability. Since time-to-market is a crucial system issue, as frequent changes in multiple location and rapid obsolescence are pressing problems. E/sup 2/PROMs, acting as nonvolatile memories and peripherals in up-based systems, play a growing role in presenting a solution. E/sup 2/PROM technology is divided into two major approaches. One approach is an extension of the basic floating-gate concept used in EPROMs. The other is a nitride technique called MNOS which has existed over several decades. E/sup 2/PROM system applications are discussed. The most advanced E/sup 2/PROMs today are easy-to-use single 5-V power supply, high-speed CMOS devices. It is noted that, with the obstacles of the past removed, E/sup 2/PROMs are increasingly being used in new designs.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131601015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Patient monitoring systems 病人监护系统
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93425
Bob Puers, Willy Sansen, K. U. Leuven
{"title":"Patient monitoring systems","authors":"Bob Puers, Willy Sansen, K. U. Leuven","doi":"10.1109/CMPEUR.1989.93425","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93425","url":null,"abstract":"The authors present a generalized description of a patient-monitoring system. This description covers virtually all existing systems. Emphasis is put on topics which are particularly suitable for the application of LSI and VLSI technologies, and some illustrative examples are given, ranging from ECG monitoring to implanted telemetry systems. Flowcharts, drawings, and photographs are provided.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131103319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
MOM-map-oriented machine-a partly custom-designed architecture compared to standard hardware 面向mom地图的机器——与标准硬件相比，部分定制设计的体系结构
Proceedings. VLSI and Computer Peripherals. COMPEURO 89 Pub Date : 1989-05-08 DOI: 10.1109/CMPEUR.1989.93471
R. Hartenstein, A. Hirschbiel, M. Weber
{"title":"MOM-map-oriented machine-a partly custom-designed architecture compared to standard hardware","authors":"R. Hartenstein, A. Hirschbiel, M. Weber","doi":"10.1109/CMPEUR.1989.93471","DOIUrl":"https://doi.org/10.1109/CMPEUR.1989.93471","url":null,"abstract":"The von Neumann principle has two bottlenecks: program accessing and data accessing. An innovative non-von Neumann principle eliminates one of them. Its new processor, the map-oriented machine (MOM), is compared with the von Neumann concept. The MOM is the key resource to a completely new philosophy of data processing, map-oriented processing. It does not use sequential programs since it has no program sequencer. For many applications it provides acceleration factors of up to several orders of magnitude, compared to von-Neumann-type processing. Existing computer application support tools (assemblers, compilers, operating systems, etc.) cannot be used for the MOM, since they produce sequential code. Thus, a new programming theory and new application support tools are introduced, so that MOM is based on a marriage between standard IC and application-specific IC techniques.<<ETX>>","PeriodicalId":304457,"journal":{"name":"Proceedings. VLSI and Computer Peripherals. COMPEURO 89","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116570302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
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