{"title":"Planar aluminiurn multilevel interconnection formed by electrochemical anodizing technique","authors":"V. Surganov, A. Mozalev","doi":"10.1109/MAM.1997.621070","DOIUrl":"https://doi.org/10.1109/MAM.1997.621070","url":null,"abstract":"This report describes a multilevel inter-connection technology based on selective electrochemical anodizing of aluminium and its alloys. In accordance with this technology, local areas into Al layer are transformed to insulating anodic alumina by low temperature electrochemical oxidation. Selective anodizing technique provides possibility to produce following components of planar multilevel inter-connections.","PeriodicalId":302609,"journal":{"name":"European Workshop Materials for Advanced Metallization,","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117260878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Schnabel, D. Dobuzinski, F. Wang, D. Perng, J. Gambiono, H. Palm
{"title":"Dry etch challenges of 0.25 /spl mu/m dual damascene structures","authors":"R. Schnabel, D. Dobuzinski, F. Wang, D. Perng, J. Gambiono, H. Palm","doi":"10.1109/mam.1997.621074","DOIUrl":"https://doi.org/10.1109/mam.1997.621074","url":null,"abstract":"Interconnects for integrated circuits are generally formed by reactive ion etching (RIE) of the metal stack. However, this process is susceptible to shorts between neighboring lines due to either incomplete etching of the stack or electrically conducting etch by products. As a result, there has been much recent interest in using damascene processes (where chemical-mechanical polishing (CMP) is used to form the metal lines) to fabricate interconnects at dimensions of 0.25 /spl mu/m and less. The damascene process has a number of benefits; the lines are defined by oxide RIE, which is considerably simpler than RIE of a multilayer metal stack. The metal CMP process provides a nearly planar surface, eliminating the need for good gap fill by the interlevel dielectrics. Finally, the metal fill of the interconnects and vias can be combined into one step (i.e. dual damascene), resulting in reduced cost.","PeriodicalId":302609,"journal":{"name":"European Workshop Materials for Advanced Metallization,","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123849502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modification of Al-based metallization for improved surface morphology","authors":"M. Zaborowski, A. Barcz","doi":"10.1109/mam.1997.621089","DOIUrl":"https://doi.org/10.1109/mam.1997.621089","url":null,"abstract":"Aluminum and some of its alloys are commonly used as metallization for silicon integrated circuits. Due to miniaturization, the critical dimensions of metallization such as line width, contact or via area in ULSI devices, are now approaching the size of a grain in the polycrystalline Al film. Particularly unwanted are hillocks i.e. large grains that outgrow above the initial Al surface. It is generally accepted that hillock growth is related to plastic flow and grain boundary diffusion where the supply of atoms takes place at the bottom of the hillock. The aim of this work is to investigate the possibilities of reduction of the density and/or the size of the hillocks by introducing into the metallization adequate barriers suppressing the grain boundary diffusion.","PeriodicalId":302609,"journal":{"name":"European Workshop Materials for Advanced Metallization,","volume":"102-103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124011555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Influence of carrier gas on Cu nucleation, film properties and MOCVD reaction kinetics","authors":"J. Rober, S. Riedel, S. Schulz, T. Gessner","doi":"10.1109/mam.1998.887499","DOIUrl":"https://doi.org/10.1109/mam.1998.887499","url":null,"abstract":"Copper CVD has been investigated for a few years as a key process for copper metallization technology among others because of its capability for high step coverage and low process temperatures. Beside low resistivity a high film growth rate, along with strong adhesion of the Cu film to the underlayer are essential for practical use in fabrication line. This paper presents the effect of carrier gas and precursor composition on the characteristics of copper MOCVD using the Cu(hfac)TMVS precursor.","PeriodicalId":302609,"journal":{"name":"European Workshop Materials for Advanced Metallization,","volume":"165 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122296068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"WNx/W as a low-resistance gate material and local interconnect","authors":"C. Galewski, P. Gadgil, L. Matthysse, C. Sans","doi":"10.1109/mam.1997.621069","DOIUrl":"https://doi.org/10.1109/mam.1997.621069","url":null,"abstract":"In this study we propose the use of an in-situ deposition of an interfacial WN, film to enable the use of W as a low resistance gate and local interconnect layer. We have found that the interfacial WN, layer greatly improves the adhesion and nucleation of the following W deposition. Furthermore, the interfacial WN, stabilizes the W to Si interface. preventing any silicide formation during anneals up to 850OC. The effect of the WN, interface layer was investigated by using a process split as shown infigure 1. The depositions were performed in the same process module with only a change in the recipe to either include, or exclude, the WN, deposition step. The composition of the WN, film was WNO and the thickness range investigated was from 50 to 200 A. Sheet resistance of the composite WN,N film is in the range of 1 to 2 ohms/square, depending on the thickness of WN, used.","PeriodicalId":302609,"journal":{"name":"European Workshop Materials for Advanced Metallization,","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125531854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}