Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)最新文献

Voltage dependence and AC life time of PMOS HCI PMOS HCI的电压依赖性和交流寿命

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599257

J. Jia, Patty Liu, Fengliang Xue, Jon Tien, Alex Cai, F. Dhaoui, P. Singaraju, F. Hawley, J. Mccollum

{"title":"Voltage dependence and AC life time of PMOS HCI","authors":"J. Jia, Patty Liu, Fengliang Xue, Jon Tien, Alex Cai, F. Dhaoui, P. Singaraju, F. Hawley, J. Mccollum","doi":"10.1109/IPFA.2013.6599257","DOIUrl":"https://doi.org/10.1109/IPFA.2013.6599257","url":null,"abstract":"In this work, HCI effect of PMOS FETs was studied. For a given drain bias, electron trapping is the dominant degradation mechanism for a gate bias close to 20% of the drain bias. A maximum gate current is seen under this bias condition. Hole trapping is dominant when the gate bias is equal to the drain bias where drain current is the maximum. Electron trapping enhances PMOS driving current or Idsat whereas hole trapping degrades Idsat. The effect of electron trapping and hole trapping cancel each other. As a result, life time is longer when two trapping mechanisms are involved compared with the life time with one trapping mechanism. In this study, device Idsat degradation was measured with different gate and drain biases in a DC mode. An AC stress is also performed in which gate/drain bias waveforms follow those of a typical switching inverter. Due to the above-mentioned cancelling effect, PMOS HCI AC life time is longer and the DC to AC conversion factor is much larger than conventionally used values. The effect of STI stress on HCI degradation is briefly studied. Layouts to minimize this effect are then proposed.","PeriodicalId":301935,"journal":{"name":"Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129868042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Analysis of dynamic retention characteristics of NWL scheme in high density DRAM 高密度DRAM中NWL方案的动态保持特性分析

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599242

Myungjae Lee, H. Kwon, Jonghyoung Lim, H. Hwang, Seongjin Jang, Y. Roh

引用次数: 2

Failure analysis for via with solder bubble 带焊泡的通孔失效分析

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599274

W. Yang, Luo Daojun

引用次数: 0

Development of failure analysis technique for temperature dependent failures 温度相关失效分析技术的发展

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599224

N. Hat, Andrew C. Sabate, Khairul Aiman Yusof

引用次数: 1

A non destructive scan diagnosis based fault isolation technique verification method using infrared laser stimulation on wafer level 一种基于无损扫描诊断的故障隔离技术——基于晶片级红外激光刺激的验证方法

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599123

G. F. You, S. Goh, B. Yeoh, Hai Hu, N. Chung, T. Fei, C. Yap, T. Lim, J. Lam

引用次数: 2

Bias-temperature instability of Si and Si(Ge)-channel sub-1nm EOT p-MOS devices: Challenges and solutions Si和Si(Ge)通道亚1nm EOT p-MOS器件的偏温不稳定性:挑战和解决方案

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599124

G. Groeseneken, M. Aoulaiche, M. Cho, J. Franco, B. Kaczer, T. Kauerauf, J. Mitard, L. Ragnarsson, P. Roussel, M. Toledano-Luque

{"title":"Bias-temperature instability of Si and Si(Ge)-channel sub-1nm EOT p-MOS devices: Challenges and solutions","authors":"G. Groeseneken, M. Aoulaiche, M. Cho, J. Franco, B. Kaczer, T. Kauerauf, J. Mitard, L. Ragnarsson, P. Roussel, M. Toledano-Luque","doi":"10.1109/IPFA.2013.6599124","DOIUrl":"https://doi.org/10.1109/IPFA.2013.6599124","url":null,"abstract":"In this paper we review the Negative-Bias-Temperature-Instability performance of Si and Si(Ge) sub 1-nanometer EOT p-MOS devices. It is shown that NBTI degradation in Si-devices follows an iso-electric field model in over 1-nanometer EOT due to the degradation mechanism of Si/SiO2 interface state generation combined with the hole trapping mechanism. However in sub 1-nanometer EOT regime, the probability of hole trapping into the gate dielectric increases and it is strongly dependent on the thickness of the interfacial oxide layer. The bulk defects affecting the NBTI are shown to be mostly pre-existing defects, though the permanently generated defects are relatively higher in sub 1-nanometer EOT devices. It is demonstrated that a minimum interfacial layer thickness of 0.4nm is required to prevent the accelerated NBTI degradation by increased direct tunneling.Si(Ge) devices, on the other hand, show a significantly reduced Negative-Bias-Temperature-Instability, by which they promise to virtually eliminate this reliability issue for ultra-thin EOT devices. So far it seems to be the only available and reliable solution for sub-1nm EOT devices. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and of a SiO2/HfO2 dielectric stack is understood in terms of a favorable energy decoupling between the SiGe channel and the gate dielectric defects. We also demonstrate that in both Si and Si(Ge) nanoscale devices the NBTI degradation shows an increasingly stochastic stepwise behavior, which leads to a time-dependent variability. Again for Si(Ge) devices a significantly reduced time-dependent variability of nanoscale devices is observed. This time-dependent variability has to be taken into account when predicting the lifetime of the technology.","PeriodicalId":301935,"journal":{"name":"Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116276519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

A new failure analysis approach to predict and localize defects and weakness areas in trough-glass-vias for a multifunctional package level camera 多功能封装级相机玻璃通孔缺陷和薄弱区域预测与定位的失效分析新方法

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599196

A. El Amrani, M. Bouya, Y. Bouissa, A. Benali, M. Faqir, M. Ghogho, A. Hadjoudja, L. Hlou

引用次数: 3

Channel Hot-Carrier degradation characteristics and trap activities of high-k/metal gate nMOSFETs 高k/金属栅极nmosfet的通道热载流子退化特性和陷阱活性

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599248

Weichun Luo, Hong Yang, Wenwu Wang, Hao Xu, Shangqing Ren, Bo Tang, Zhaoyun Tang, Jing Xu, Jiang Yan, Chao Zhao, Dapeng Chen, Ye Tianchun

引用次数: 2

Modelling of LED light source reliability LED光源可靠性建模

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599163

G. Tao

引用次数: 9

Failure analysis considerations in designing for EOS/ESD robustness EOS/ESD稳健性设计中的失效分析考虑

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599128

J. Hajjar, A. Righter, Ed Wolfe, A. Olney

引用次数: 1