Bias-temperature instability of Si and Si(Ge)-channel sub-1nm EOT p-MOS devices: Challenges and solutions

Abstract

In this paper we review the Negative-Bias-Temperature-Instability performance of Si and Si(Ge) sub 1-nanometer EOT p-MOS devices. It is shown that NBTI degradation in Si-devices follows an iso-electric field model in over 1-nanometer EOT due to the degradation mechanism of Si/SiO2 interface state generation combined with the hole trapping mechanism. However in sub 1-nanometer EOT regime, the probability of hole trapping into the gate dielectric increases and it is strongly dependent on the thickness of the interfacial oxide layer. The bulk defects affecting the NBTI are shown to be mostly pre-existing defects, though the permanently generated defects are relatively higher in sub 1-nanometer EOT devices. It is demonstrated that a minimum interfacial layer thickness of 0.4nm is required to prevent the accelerated NBTI degradation by increased direct tunneling.Si(Ge) devices, on the other hand, show a significantly reduced Negative-Bias-Temperature-Instability, by which they promise to virtually eliminate this reliability issue for ultra-thin EOT devices. So far it seems to be the only available and reliable solution for sub-1nm EOT devices. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and of a SiO2/HfO2 dielectric stack is understood in terms of a favorable energy decoupling between the SiGe channel and the gate dielectric defects. We also demonstrate that in both Si and Si(Ge) nanoscale devices the NBTI degradation shows an increasingly stochastic stepwise behavior, which leads to a time-dependent variability. Again for Si(Ge) devices a significantly reduced time-dependent variability of nanoscale devices is observed. This time-dependent variability has to be taken into account when predicting the lifetime of the technology.