Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)最新文献_第10页

Understanding correlated drain and gate current fluctuations 理解相关的漏极和栅极电流波动

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599125

W. Goes, M. Toledano-Luque, O. Baumgartner, M. Bina, F. Schanovsky, B. Kaczer, T. Grasser

{"title":"Understanding correlated drain and gate current fluctuations","authors":"W. Goes, M. Toledano-Luque, O. Baumgartner, M. Bina, F. Schanovsky, B. Kaczer, T. Grasser","doi":"10.1109/IPFA.2013.6599125","DOIUrl":"https://doi.org/10.1109/IPFA.2013.6599125","url":null,"abstract":"Recently, some experimental groups have observed the occurrence of correlated drain and gate current fluctuations, which indicate that both currents are influenced by the charge state of the same defect. Since the physical reason behind this phenomenon is unclear at the moment, we evaluated two different explanations: The first model assumes that direct tunneling of carriers is affected by the electrostatic field of the charged defect. Interestingly, this model inherently predicts the gate bias and temperature dependences observed in the experiments and is therefore quite promising at a first glance. In the second model, our multi-state defect model is employed to describe trap-assisted tunneling as a combination of two consecutive nonradiative multi-phonon transitions - namely hole capture from the substrate followed by hole emission into the poly-gate. The latter transition is found to be in the weak electron-phonon coupling regime, which requires the consideration of all band states instead of only the band edges. Our investigation shows that the electrostatic model must be discarded since it predicts only small changes in the gate current while the extended variant of the multi-state defect model delivers quite promising results.","PeriodicalId":301935,"journal":{"name":"Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114430175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

Characteristic analysis of total dose irradiation annealing effect in SOI NMOSFET SOI NMOSFET中总剂量辐照退火效应特性分析

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599266

He Yujuan, Lu Hongwei, En Yunfei

引用次数: 0

Failure analysis of a 2.5D stacking using μinsert technology 基于μinsert技术的2.5D堆叠失效分析

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599194

A. Nowodzinski, V. Mandrillon, D. Bouchu, R. Franiatte, H. Boutry, D. Bloch, K. Rousseau, C. Lionel

引用次数: 0

Putting the die contour back - Methods in advanced sample preparation for 3D and flip-chip devices 把模具轮廓放回原位——三维和倒装芯片的高级样品制备方法

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599203

C. Richardson, G. Liechty, Clay Smith, Michael Karow

引用次数: 3

Failure rate calculation for NMOS devices under multiple failure mechanisms 多种失效机制下NMOS器件的故障率计算

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599182

Zhenwei Zhou, Xin Liu, Q. Shi, Yunfei En, Xiaohan Wang

引用次数: 4

High resolution Magnetic Current Imaging for die level short localization 用于模具级短定位的高分辨率磁流成像

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599179

J. Gaudestad, N. Gagliolo, V. Talanov, R. H. Yeh, C. B. Ma

引用次数: 14

Charge pumping in floating-body SOI FinFETs 浮体SOI finfet中的电荷泵送

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599158

D. Fleetwood, E. Zhang

引用次数: 0

Electrical properties of N-type CdS and P-type CdTe thin films in CdS/CdTe solar cells n型CdS和p型CdTe薄膜在CdS/CdTe太阳能电池中的电学性能

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599187

Jingjin Wu, F. Ang, Cezhou Zhao, Jeremy Smith

引用次数: 3

A study of latch-up mechanisms for adjacent pins on multiple power supply circuits 多电源电路中相邻引脚锁存机制的研究

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599130

S. Liang, A. Guo, J. Ji, Jason Chen, J. Su, Juley Wang, Jeff Wu, Johnson Lin

{"title":"A study of latch-up mechanisms for adjacent pins on multiple power supply circuits","authors":"S. Liang, A. Guo, J. Ji, Jason Chen, J. Su, Juley Wang, Jeff Wu, Johnson Lin","doi":"10.1109/IPFA.2013.6599130","DOIUrl":"https://doi.org/10.1109/IPFA.2013.6599130","url":null,"abstract":"Traditional latch-up (VDD-to-VSS) in CMOS IC's is formed by the parasitic p-n-p-n structure between VDD and VSS. In modern technologies, although the guard rings and substrate/ well pickups could efficiently overcome the latch-up failure in CMOS ICs, the latch-up failure phenomenon is still existed in many special application circuits. With mixed signal design requirements, there are more than 2 kinds of devices that are deployed in one chip to implement the design with higher voltage system on the advanced technologies with lower voltage application in the mixed-voltage process. Therefore, these comprehensive process and design approaches could provide more flexibility for the chips to be connected with older system [1-2]. A latch-up phenomenon is reported here that the latch-up current path occurs between adjacent power pins of 65nm process, IO circuit is powered by different power supplies. In this product, IO circuitry is with 3.3V and core circuitry is with 1.2V power supply. Because there is no VDD-to-VDD latch-up rule, the 3.3V n-well to 1.2V n-well space was <; 10 um (note: without any guard rings in between). Latch-up immunity of I/O pins resulted from a higher substrate potential required on the base-emitter junction forward bias of LQpnp.","PeriodicalId":301935,"journal":{"name":"Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125524102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

ISTFA best paper: FemtoFarad/TeraOhm endpoint detection for microsurgery of integrated circuit devices 最佳论文:微外科集成电路器件的飞法拉/太奥端点检测

Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) Pub Date : 2013-07-15 DOI: 10.1109/IPFA.2013.6599192

J. Colvin

引用次数: 2