2011 IEEE International Symposium on Hardware-Oriented Security and Trust最新文献

Formal security evaluation of hardware Boolean masking against second-order attacks 硬件布尔屏蔽抗二阶攻击的形式化安全评估

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5954993

Houssem Maghrebi, S. Guilley, J. Danger

{"title":"Formal security evaluation of hardware Boolean masking against second-order attacks","authors":"Houssem Maghrebi, S. Guilley, J. Danger","doi":"10.1109/HST.2011.5954993","DOIUrl":"https://doi.org/10.1109/HST.2011.5954993","url":null,"abstract":"The masking countermeasure in hardware has been widely studied, for its simplicity and its efficiency. Notably, no care is required at backend level and the throughput is not affected with respect to an unprotected implementation. In this article, we are concerned with a formal security evaluation of Boolean hardware masking schemes. Following a practice-oriented evaluation framework introduced at EURO-CRYPT'2009 [22], we compute both leakage and attack metrics. The hardware implementations have the specificity that the signal to noise ratio is below 1. In this particular case, we prove that a leakage metric (namely the mutual information) allows to characterize perfectly the best attack. This was previously unknown; moreover, we exhibit explicitly the links between leakage and attacks metrics. This result is in line with [10] but conflicts with [24]. More precisely, second-order DPA with a centered product combination function yields the largest leaks and the most powerful attacks. However, those are not possible if the implementation is “zero-offset”, an implementation of first-order masking only possible in hardware. Furthermore, even the sub-optimal attacks are impeded, due to the high noise that characterizes parallel hardware crypto-processors. Therefore, masked implementations in hardware reach much higher security levels than software counterparts while not degrading significantly the computation throughput.","PeriodicalId":300377,"journal":{"name":"2011 IEEE International Symposium on Hardware-Oriented Security and Trust","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116866913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Algorithmic collision analysis for evaluating cryptographic systems and side-channel attacks 评估密码系统与旁信道攻击的算法冲突分析

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5955000

Q. Luo, Yunsi Fei

引用次数: 23

Reliable and efficient PUF-based key generation using pattern matching 使用模式匹配可靠和高效的基于puf的密钥生成

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5955010

Zdenek Sid Paral, S. Devadas

{"title":"Reliable and efficient PUF-based key generation using pattern matching","authors":"Zdenek Sid Paral, S. Devadas","doi":"10.1109/HST.2011.5955010","DOIUrl":"https://doi.org/10.1109/HST.2011.5955010","url":null,"abstract":"We describe a novel and efficient method to reliably provision and re-generate a finite and exact sequence of bits, for use with cryptographic applications, e.g., as a key, by employing one or more challengeable Physical Unclonable Function (PUF) circuit elements. Our method reverses the conventional paradigm of using public challenges to generate secret PUF responses; it exposes response patterns and keeps secret the particular challenges that generate response patterns. The key is assembled from a series of small (initially chosen or random), secret integers, each being an index into a string of bits produced by the PUF circuit(s); a PUF unique pattern at each respective index is then persistently stored between provisioning and all subsequent key re-generations. To obtain the secret integers again, a newly repeated PUF output string is searched for highest-probability matches with the stored patterns. This means that complex error correction logic such as BCH decoders are not required. The method reveals only relatively short PUF output data in public store, thwarting opportunities for modeling attacks. We provide experimental results using data obtained from PUF ASICs, which show that keys can be efficiently and reliably generated using our scheme under extreme environmental variation.","PeriodicalId":300377,"journal":{"name":"2011 IEEE International Symposium on Hardware-Oriented Security and Trust","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121596598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 106

Practical evaluation of DPA countermeasures on reconfigurable hardware 可重构硬件上DPA对抗的实际评估

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5955014

A. Moradi, Oliver Mischke, C. Paar

引用次数: 14

A fast power current analysis methodology using capacitor charging model for side channel attack evaluation 一种基于电容充电模型的快速电源电流分析方法，用于侧通道攻击评估

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5955002

Daisuke Fujimoto, M. Nagata, T. Katashita, A. Sasaki, Y. Hori, Akashi Satoh

引用次数: 11

Accelerating early design phase differential power analysis using power emulation techniques 使用功率仿真技术加速早期设计阶段差分功率分析

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5955001

Armin Krieg, Christian Bachmann, J. Grinschgl, C. Steger, R. Weiss, J. Haid

{"title":"Accelerating early design phase differential power analysis using power emulation techniques","authors":"Armin Krieg, Christian Bachmann, J. Grinschgl, C. Steger, R. Weiss, J. Haid","doi":"10.1109/HST.2011.5955001","DOIUrl":"https://doi.org/10.1109/HST.2011.5955001","url":null,"abstract":"The personal banking and ID sector has seen a tremendous change in recent years, partially caused by the widespread introduction of smart-cards. Because of the extensive implications of a successful attack on these devices, a wide range of practical as well as purely academic attacks has been developed during the last years. These attacks have unveiled weaknesses in hardware as well as software implementations of several different, partially widely used cryptographic algorithms. An especially powerful method, the differential power analysis (DPA), extracts secret information from power consumption and electro-magnetic emission profiles. The efficiency of a DPA attack significantly depends on the quality of the cryptographic algorithm implementation. These traces currently can only be generated using real hardware or simulation-based approaches. Depending on the chosen simulation accuracy these evaluations result in time-consuming RTL and SPICE simulations often limiting the maximum amount of available execution traces. This paper introduces a novel high-speed methodology for early security evaluations of integrated processor systems using power emulation. First, the usage of power emulation hardware allows for the estimation of attack effort that an adversary will have to invest to gain secret information from an algorithm's execution profile. Second, countermeasures against differential power analysis attacks can be quickly evaluated in terms of effectiveness. The shown approach uses semi-automatic characterization techniques and fully synthesizable emulation hardware to reduce the designer's dependency on time-consuming simulation runs.","PeriodicalId":300377,"journal":{"name":"2011 IEEE International Symposium on Hardware-Oriented Security and Trust","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127083874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

ODETTE: A non-scan design-for-test methodology for Trojan detection in ICs ODETTE:用于ic中特洛伊木马检测的非扫描设计测试方法

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5954989

Mainak Banga, M. Hsiao

引用次数: 46

Case study: Detecting hardware Trojans in third-party digital IP cores 案例研究:检测第三方数字IP核中的硬件木马

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5954998

Xuehui Zhang, M. Tehranipoor

引用次数: 205

TrustGeM: Dynamic trusted environment generation for chip-multiprocessors TrustGeM:用于芯片多处理器的动态可信环境生成

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5954994

L. A. Bathen, N. Dutt

{"title":"TrustGeM: Dynamic trusted environment generation for chip-multiprocessors","authors":"L. A. Bathen, N. Dutt","doi":"10.1109/HST.2011.5954994","DOIUrl":"https://doi.org/10.1109/HST.2011.5954994","url":null,"abstract":"Embedded system security challenges have been exacerbated by the complexity inherent in the software stack of next generation handheld devices (internet connectivity, app stores, mobile banking, etc.) and the aggressive push for multicore technology. As applications with different degrees of assurance are deployed on these multiprocessor platforms, new challenges emerge in terms of protection against software based side channel attacks and exploits such as buffer overruns. In this paper, we introduce TrustGeM: a dynamic trusted environment generation engine for chip-multiprocessors. TrustGeM's goal is to dynamically generate trusted execution environments for applications with different assurance requirements. TrustGeM exploits the concepts of application driven policy generation, performance/power-aware on-chip application sandboxing, and reliable, secure, and dynamic memory virtualization. Experimental results on an 8 Core CMP show that TrustGeM is able reduce overall system energy by an average 24% due to its memory utilization efficiency while incurring minimal performance overhead over the ideal case (an average of 5%). TrustGeM is also able to generate policies with much smaller memory requirements allowing the dynamic trusted environment generation to enforce the policies much more efficiently.","PeriodicalId":300377,"journal":{"name":"2011 IEEE International Symposium on Hardware-Oriented Security and Trust","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115275863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Systematic security evaluation method against C safe-error attacks 针对C安全错误攻击的系统安全评估方法

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5954997

Dusko Karaklajic, Junfeng Fan, I. Verbauwhede

引用次数: 1