A fast power current analysis methodology using capacitor charging model for side channel attack evaluation

Abstract

Fast power current analysis method using capacitor charging model was introduced to evaluate security of cryptographic hardware against side channel attacks before the circuit is fabricated as an LSI chip. The method was applied to CPA (Correlation Power Analysis) on various AES (Advanced Encryption Standard) circuits, which require more than 10,000 power current traces, and simulation speed was accelerated by 40–60 times in comparison with conventional full transistor level analysis. The proposed simulation based CPA revealed all of the secret keys of the AES circuits by extracting capacitance model from the post-layout data using a 65-nm CMOS standard cell library. The layout was also fabricated as an LSI chip, and CPA on the LSI was conducted. The results showed remarkable consistency between simulation and actual measurement in terms of information leakage related to the secret keys in power waveforms.