2011 IEEE International Symposium on Hardware-Oriented Security and Trust最新文献_第2页

Low-cost recovery for the code integrity protection in secure embedded processors 安全嵌入式处理器中代码完整性保护的低成本恢复

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5955004

N. Huu, B. Robisson, M. Agoyan, Nathalie Drach-Temam

引用次数: 9

On improving reliability of delay based Physically Unclonable Functions under temperature variations 温度变化下基于物理不可克隆函数的延迟可靠性提高研究

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5955012

Raghavan Kumar, Harikrishnan Chandrikakutty, S. Kundu

{"title":"On improving reliability of delay based Physically Unclonable Functions under temperature variations","authors":"Raghavan Kumar, Harikrishnan Chandrikakutty, S. Kundu","doi":"10.1109/HST.2011.5955012","DOIUrl":"https://doi.org/10.1109/HST.2011.5955012","url":null,"abstract":"Physically Unclonable Functions (PUFs) are a special class of circuits used for challenge-response authentication. The challenge-response pair for PUFs should be mathematically unpredictable, but must be reliable and remain unvarying. The reliability of PUFs implemented in CMOS circuits is frequently compromised by environmental conditions such as voltage and temperature. In this paper, we propose two methods for improving the reliability of delay based PUFs, by reducing temperature sensitivity. The first method focuses on improving the gate overdrive (VGS − Vt(T)), by operating the PUF at an optimized supply voltage (V′DD), also called as ZTC (Zero Temperature Coefficient) voltage. The optimum supply voltage for a 24 stage PUF is almost 23% lower than the nominal supply voltage in 45nm CMOS technology. The second method exploits the negative temperature coefficient (TCR) property of n+ and p+ polysilicon placed as source feedback resistors. A 16% improvement in reliability has been demonstrated for both the methods. Moreover, we also demonstrate that these design optimizations do not compromise the PUF uniqueness.","PeriodicalId":300377,"journal":{"name":"2011 IEEE International Symposium on Hardware-Oriented Security and Trust","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123173175","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 31

Security challenges and opportunities in adaptive and reconfigurable hardware 自适应和可重构硬件中的安全挑战和机遇

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5954986

Victor Costan, S. Devadas

引用次数: 10

TinyTPM: A lightweight module aimed to IP protection and trusted embedded platforms TinyTPM:一个轻量级模块，旨在IP保护和可信的嵌入式平台

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5954987

Thomas Feller, Sunil Malipatlolla, David Meister, S. Huss

引用次数: 19

Performance evaluation of protocols resilient to physical attacks 抗物理攻击协议的性能评估

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5954995

S. Guilley, L. Sauvage, J. Danger, Nidhal Selmane, Denis Réal

{"title":"Performance evaluation of protocols resilient to physical attacks","authors":"S. Guilley, L. Sauvage, J. Danger, Nidhal Selmane, Denis Réal","doi":"10.1109/HST.2011.5954995","DOIUrl":"https://doi.org/10.1109/HST.2011.5954995","url":null,"abstract":"Cryptographic implementations are vulnerable to physical attacks. Many countermeasures to resist them have been proposed in the past. However, they are all specific to a given attacker and allow to mitigate the risk only up to a certain level: improved attacks on those countermeasures can most of the time be devised. Therefore, a new trend consists in making cryptographic implementations resilient to physical attacks. This strategy makes it possible to prove the countermeasure against all possible types of attackers captured by a security model. Several resilient schemes for the protection of block ciphers exist. For a given security objective, they all permit to reach the same security level. Therefore, they differentiate only according to their efficiency. We first show that the genuine versions of these protocols achieve different I/O bandwidth and computational performance. Our second contribution is to improve those protocols thanks to a message blinding, assuming passive attacks require more than two traces to be successful. Then, we bring as a third contribution the fact that the improved versions of the protocols are very much alike, and that the difference between them depends only from the specific details of their instantiation.","PeriodicalId":300377,"journal":{"name":"2011 IEEE International Symposium on Hardware-Oriented Security and Trust","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131810242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

New security threats against chips containing scan chain structures 针对包含扫描链结构的芯片的新安全威胁

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5955005

Jean DaRolt, G. D. Natale, M. Flottes, B. Rouzeyre

引用次数: 74

TeSR: A robust Temporal Self-Referencing approach for Hardware Trojan detection 一种用于硬件木马检测的健壮的时间自引用方法

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5954999

S. Narasimhan, Xinmu Wang, Dongdong Du, R. Chakraborty, S. Bhunia

{"title":"TeSR: A robust Temporal Self-Referencing approach for Hardware Trojan detection","authors":"S. Narasimhan, Xinmu Wang, Dongdong Du, R. Chakraborty, S. Bhunia","doi":"10.1109/HST.2011.5954999","DOIUrl":"https://doi.org/10.1109/HST.2011.5954999","url":null,"abstract":"Malicious modification of integrated circuits, referred to as Hardware Trojans, in untrusted fabrication facility has emerged as a major security threat. Logic testing approaches are not very effective for detecting large sequential Trojans which require multiple state transitions often triggered by rare circuit events in order to activate and cause malfunction. On the other hand, side-channel analysis has emerged as an effective approach for detection of such large sequential Trojans. However, existing side-channel approaches suffer from large reduction in detection sensitivity with increasing process variations or decreasing Trojan size. In this paper, we propose TeSR, a Temporal Self-Referencing approach that compares the current signature of a chip at two different time windows to completely eliminate the effect of process noise, thus providing high detection sensitivity for Trojans of varying size. Furthermore, unlike existing approaches, it does not require golden chip instances as a reference. Simulation results for three complex designs and three representative sequential Trojan circuits demonstrate the effectiveness of the approach under large inter- and intra-die process variations.","PeriodicalId":300377,"journal":{"name":"2011 IEEE International Symposium on Hardware-Oriented Security and Trust","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126884796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 129

Security Checkers: Detecting processor malicious inclusions at runtime 安全检查器:在运行时检测处理器恶意包含

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5954992

Michael Bilzor, Ted Huffmire, C. Irvine, T. Levin

引用次数: 38

Flexible architecture optimization and ASIC implementation of group signature algorithm using a customized HLS methodology 灵活的架构优化和使用定制HLS方法的组签名算法的ASIC实现

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5954996

S. Morioka, Toshiyuki Isshiki, Satoshi Obana, Yuichi Nakamura, Kazue Sako

{"title":"Flexible architecture optimization and ASIC implementation of group signature algorithm using a customized HLS methodology","authors":"S. Morioka, Toshiyuki Isshiki, Satoshi Obana, Yuichi Nakamura, Kazue Sako","doi":"10.1109/HST.2011.5954996","DOIUrl":"https://doi.org/10.1109/HST.2011.5954996","url":null,"abstract":"Group signature is one of the main theme in recent digital signature studies. Typical signature algorithm is a combination of more than 70 elliptic curve (ECC), modular (RSA), long-bit integer and hash arithmetic functions. A full H/W IP core is strongly desired for the use of group signature in SoCs in slow-clock and low-power mobile devices and embedded systems. Flexible adjustment of H/W speed and size, depending on different systems and LSI process technologies, is also required. However, for designing and verifying H/W, the group signature algorithm is too complicated to use a standard RTL (Register Transfer Level) design methodology nor any recent HLS (High Level Synthesis). Therefore, we incorporated a two-level behavioral synthesis approach, where an optimized macro-architecture is explored by a custom-made scheduler, after a database of multiple number of microarchitectures are effectively constructed by conventional HLS. We implemented the signature algorithm on a low-cost 0.25um gate-array. The H/W size is approximately 1M gates and our chip can compute a group signature at the equivalent speed (0.135 seconds@100MHz clock) with 3GHz PC S/W, while the power consumption is two orders of magnitude lower (425mW@100MHz).","PeriodicalId":300377,"journal":{"name":"2011 IEEE International Symposium on Hardware-Oriented Security and Trust","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129884778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Placement of trust anchors in embedded computer systems 嵌入式计算机系统中信任锚的放置

2011 IEEE International Symposium on Hardware-Oriented Security and Trust Pub Date : 2011-06-05 DOI: 10.1109/HST.2011.5955006

S. Papa, W. Casper, S. Nair

引用次数: 9