Proceedings European Design and Test Conference. ED & TC 97最新文献

Optimal scheduling for fast systolic array implementations 快速收缩阵列实现的最优调度

Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582433

I. Ozimek, R. Verlic, J. Tasic

引用次数: 1

High-speed C-testable systolic array design for Galois-field inversion 用于伽罗瓦场反演的高速c -可测试收缩阵列设计

Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582380

Chih-Tsun Huang, Cheng-Wen Wu

引用次数: 15

A monolithic off-chip IDDQ monitor 单片IDDQ监视器

Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582442

M. Svajda, B. Straka, H. Manhaeve

引用次数: 1

Improving the accuracy of support-set finding method for power estimation of combinational circuits 提高组合电路功率估计中支持集查找方法的精度

Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582411

Hoon Choi, S. Hwang

引用次数: 5

Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections 边界扫描架构的扩展和BIST的新思想，使互连更有效的测试和自测试

Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582443

A. Kristof

引用次数: 0

A real-time smart sensor system for visual motion estimation 用于视觉运动估计的实时智能传感器系统

Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582445

T. Röwekamp, L. Peters

引用次数: 2

Performance verification using partial evaluation and interval analysis 使用部分评估和区间分析进行性能验证

Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582435

J. Walrath, R. Vemuri, William Bradley

{"title":"Performance verification using partial evaluation and interval analysis","authors":"J. Walrath, R. Vemuri, William Bradley","doi":"10.1109/EDTC.1997.582435","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582435","url":null,"abstract":"Summary form only given. A performance model for a typical design represented in a high-level description language can be generated by augmenting the design components with attributes and evaluation rules. An attribute represents some performance aspect of a design that can be either assigned a base initial value or calculated using an evaluation rule. Heat dissipation, dynamic power consumption, and maximum throughput rate are just a few examples of various performance aspects that can be represented with attributes. Evaluation rules contained in the performance model can be classified as either equational or procedural. An equational performance model is a model containing only evaluation rules that are composed of mathematical operations such as addition, subtraction, and so forth. Likewise, a procedural performance model may contain equational rules, but it also has rules composed of complex programming constructs such as an assignment statement, if-then-else, case, and while control constructs and procedure calls. Our method for performance verification involves placing relational constraints on attributes in the performance model and determining whether all constraints can be satisfied simultaneously. Interval mathematics provides a convenient technique to represent relational constraints as intervals. Each attribute has an initial interval from negative infinity to positive infinity. Further constraints are specified by the user, the interval analysis technique is applied, and a verification result is produced.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121677219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Analogue layout generation by World Wide Web server-based agents 基于万维网服务器的代理生成模拟布局

Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582387

L. T. Walczowski, D. Nalbantis, W. Waller, K. Shi

引用次数: 3

Deep sub-micron I/sub DDQ/ testing: issues and solutions 深亚微米I/sub DDQ/测试:问题及解决方案

Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582370

M. Sachdev

引用次数: 69

Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks 面向控制的同步网络功率优化时钟门控逻辑的符号综合

Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582409

L. Benini, G. Micheli, E. Macii, M. Poncino, R. Scarsi

{"title":"Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks","authors":"L. Benini, G. Micheli, E. Macii, M. Poncino, R. Scarsi","doi":"10.1109/EDTC.1997.582409","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582409","url":null,"abstract":"Recent results have shown that clock-gating techniques are effective in reducing the total power consumption of sequential circuits. Unfortunately, such techniques assume the availability of the state transition graph of the target system, and rely on explicit algorithms whose complexity is polynomial in the number of states, that is, exponential in the number of state variables. This assumption poses serious limitations on the size of the circuits for which automatic gated-clock generation is feasible. In this paper we propose fully symbolic algorithms for the automatic extraction and synthesis of the clock-gating circuitry for large control-oriented sequential designs. Our techniques leverage the compact BDD-based representation of Boolean and pseudo-Boolean functions to extend the applicability of gated-clock architectures to designs implemented by synchronous networks. As a result, we can deal with circuits for which the explicit state transition graph is too large to be generated and/or manipulated. Moreover, symbolic manipulation techniques allow accurate probabilistic computations; in particular, they enable the use of non-equiprobable primary input distributions, a key step in the construction of models that match the behavior of real hardware devices with a high degree of fidelity. The results are encouraging, since power savings of up to 36% have been obtained on controllers containing up to 21 registers.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130086665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 38