High-speed C-testable systolic array design for Galois-field inversion

Abstract

Systolic architectures for inversion in Galois field (GF(2/sup m/)) are presented. The proposed inversion algorithm is a counter-free extended Euclidean algorithm, which results in simple circuit implementation for GF inversion. Additionally, the bit-parallel implementation proposed is shown to be C-testable. Testability and modularity make it suited to VLSI implementation.