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Proceedings European Design and Test Conference. ED & TC 97最新文献

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Scheduling using mixed arithmetic: an ILP formulation 混合算法调度:一个ILP公式
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582434
A. Mignotte, O. Peyran
{"title":"Scheduling using mixed arithmetic: an ILP formulation","authors":"A. Mignotte, O. Peyran","doi":"10.1109/EDTC.1997.582434","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582434","url":null,"abstract":"Summary form only given. We present a way to automatically select, within an architectural synthesis tool, the best operand and operator number systems, in order to find the best speed/area tradeoff. This implies the use of different number systems (redundant and non-redundant) for the same design: this is what we call mixed arithmetics. We present an integer linear programming (ILP) formulation to solve a scheduling problem.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130443292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Compact structural test generation for analog macros 模拟宏的紧凑结构测试生成
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582420
V. Kaal, H. Kerkhoff
{"title":"Compact structural test generation for analog macros","authors":"V. Kaal, H. Kerkhoff","doi":"10.1109/EDTC.1997.582420","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582420","url":null,"abstract":"A structural, fault-model based methodology for the generation of compact high-quality test sets for analog macros is presented. Results are shown for an IV-converter macro design. Parameters of so-called test configurations are optimized for detection of faults in a fault-list and an optimal selection algorithm results in determining the best test set. The distribution of the results along the parameter-axes of the test configurations is investigated to identify a collapsed high-quality test set.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114415360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Design of oscillation-based test structures for active RC filters 有源RC滤波器振荡测试结构设计
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582431
M. Zarnik, F. Novak, S. Macek
{"title":"Design of oscillation-based test structures for active RC filters","authors":"M. Zarnik, F. Novak, S. Macek","doi":"10.1109/EDTC.1997.582431","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582431","url":null,"abstract":"Summary form only given. We apply the oscillation-based test strategy to test active RC filters. We develop general guidelines for the design of the oscillation-based test structures and describe in more details the resonator active filler (biquad filter) configuration. It can be shown that some of the derived structures are achieved by simple circuit modification while for the more general case additional feedback loop network is required.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116160725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
A new quality estimation methodology for mixed-signal and analogue ICs 一种新的混合信号和模拟集成电路质量估计方法
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582419
T. Olbrich, I. Grout, Y. E. Aimine, A. Richardson, J. Contensou
{"title":"A new quality estimation methodology for mixed-signal and analogue ICs","authors":"T. Olbrich, I. Grout, Y. E. Aimine, A. Richardson, J. Contensou","doi":"10.1109/EDTC.1997.582419","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582419","url":null,"abstract":"IC product quality is commonly described as the faulty device level at shipment and is becoming an increasingly important metric in the Microelectronics Industry. This paper presents and demonstrates a quality estimation approach based on Inductive Fault Analysis for mixed-signal and analogue ICs, that quantitatively models the quality related parameters prior to production. It is shown how the approach can be used to optimise the manufacturing test program.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117184117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Library mapping for memories 内存库映射
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582372
P. Jha, N. Dutt
{"title":"Library mapping for memories","authors":"P. Jha, N. Dutt","doi":"10.1109/EDTC.1997.582372","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582372","url":null,"abstract":"We present a library mapping technique that synthesizes a source memory module from a library of target memory modules. We define the library mapping problem for memories, identify and solve the three subproblems of port, bit-width and size (word) mapping associated with this task and finally combine these solutions into an efficient memory mapping algorithm. Experimental results on a number of memory-intensive designs demonstrate that our memory mapping approach generates a wide variety of cost-effective designs, often counter-intuitive ones, based on a user-given cost function and the target library.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124644971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Retargetable generation of code selectors from HDL processor models 可从HDL处理器模型中重新生成代码选择器
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582348
R. Leupers, P. Marwedel
{"title":"Retargetable generation of code selectors from HDL processor models","authors":"R. Leupers, P. Marwedel","doi":"10.1109/EDTC.1997.582348","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582348","url":null,"abstract":"Besides high code quality, a primary issue in embedded code generation is retargetability of code generators. This paper presents techniques for automatic generation of code selectors from externally specified processor models. In contrast to previous work, our retargetable compiler RECORD does not require tool-specific modelling formalisms, but starts from general HDL processor models. From an HDL model, all processor aspects needed for code generation are automatically derived. As demonstrated by experimental results, short turnaround times for retargeting are achieved, which permits study of the HW/SW trade-off between processor architectures and program execution speed.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"384 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126731150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 75
Design and implementation of a coprocessor for cryptography applications 用于密码学应用的协处理器的设计与实现
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582361
A. Royo, Javier Moran, J. López
{"title":"Design and implementation of a coprocessor for cryptography applications","authors":"A. Royo, Javier Moran, J. López","doi":"10.1109/EDTC.1997.582361","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582361","url":null,"abstract":"In this paper, an ASIC suitable for cryptography applications based on modular arithmetic techniques, is presented. These applications, such as for example digital signature (DSA) and public key encryption and decryption (RSA) use, as basic operation, the modular exponentiation. This ASIC works as a coprocessor with a special set of instructions specialized in dealing with high accuracy integers, as well as on the rapid evaluation of modular multiplications and exponentiations. The algorithm, the hardware architecture the design methodology and the results are described in detail.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114141209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
Built-in self-test methodology for A/D converters 内置自检方法的A/D转换器
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582382
R. D. Vries, T. Zwemstra, E. Bruls, P. Regtien
{"title":"Built-in self-test methodology for A/D converters","authors":"R. D. Vries, T. Zwemstra, E. Bruls, P. Regtien","doi":"10.1109/EDTC.1997.582382","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582382","url":null,"abstract":"A (partial) Built-in Self-Test (BIST) methodology is proposed for analog to digital (A/D) converters. In this methodology the number of bits of the A/D converter that needs to be monitored externally in a test is reduced. This reduction depends, among other things, on the frequency of the applied test signal. At low test signal frequencies only the least significant bit (LSB) needs to be monitored and a \"full\" BIST becomes feasible. An analysis is made of the trade-off between the size of the on-chip test circuitry and the accuracy of this BIST technique.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130264823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 55
Application independent module generation in analog layouts 模拟布局中独立于应用程序的模块生成
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582437
M. Wolf, U. Kleine
{"title":"Application independent module generation in analog layouts","authors":"M. Wolf, U. Kleine","doi":"10.1109/EDTC.1997.582437","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582437","url":null,"abstract":"This paper presents a new feature for a module generator environment that performs application independent module description in analog layouts. With the help of a special capacitance sensitivity matrix one module description can be used for different applications.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127685924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
March LA: a test for linked memory faults 三月LA:对关联记忆错误的测试
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.5555/787260.787737
A. V. Goor, G. Gaydadjiev, V. Yarmolik, V. G. Mikitjuk
{"title":"March LA: a test for linked memory faults","authors":"A. V. Goor, G. Gaydadjiev, V. Yarmolik, V. G. Mikitjuk","doi":"10.5555/787260.787737","DOIUrl":"https://doi.org/10.5555/787260.787737","url":null,"abstract":"This paper introduces a test which can detect all simple faults as well as all linked faults, involving an arbitrary number of simple faults.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122435952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
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