发布求助
文献互助 智能选刊 最新文献

Proceedings European Design and Test Conference. ED & TC 97最新文献

筛选
英文 中文
Scheduling using mixed arithmetic: an ILP formulation 混合算法调度:一个ILP公式
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582434
A. Mignotte, O. Peyran
{"title":"Scheduling using mixed arithmetic: an ILP formulation","authors":"A. Mignotte, O. Peyran","doi":"10.1109/EDTC.1997.582434","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582434","url":null,"abstract":"Summary form only given. We present a way to automatically select, within an architectural synthesis tool, the best operand and operator number systems, in order to find the best speed/area tradeoff. This implies the use of different number systems (redundant and non-redundant) for the same design: this is what we call mixed arithmetics. We present an integer linear programming (ILP) formulation to solve a scheduling problem.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130443292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Compact structural test generation for analog macros 模拟宏的紧凑结构测试生成
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582420
V. Kaal, H. Kerkhoff
{"title":"Compact structural test generation for analog macros","authors":"V. Kaal, H. Kerkhoff","doi":"10.1109/EDTC.1997.582420","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582420","url":null,"abstract":"A structural, fault-model based methodology for the generation of compact high-quality test sets for analog macros is presented. Results are shown for an IV-converter macro design. Parameters of so-called test configurations are optimized for detection of faults in a fault-list and an optimal selection algorithm results in determining the best test set. The distribution of the results along the parameter-axes of the test configurations is investigated to identify a collapsed high-quality test set.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114415360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Design of oscillation-based test structures for active RC filters 有源RC滤波器振荡测试结构设计
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582431
M. Zarnik, F. Novak, S. Macek
{"title":"Design of oscillation-based test structures for active RC filters","authors":"M. Zarnik, F. Novak, S. Macek","doi":"10.1109/EDTC.1997.582431","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582431","url":null,"abstract":"Summary form only given. We apply the oscillation-based test strategy to test active RC filters. We develop general guidelines for the design of the oscillation-based test structures and describe in more details the resonator active filler (biquad filter) configuration. It can be shown that some of the derived structures are achieved by simple circuit modification while for the more general case additional feedback loop network is required.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116160725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
A new quality estimation methodology for mixed-signal and analogue ICs 一种新的混合信号和模拟集成电路质量估计方法
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582419
T. Olbrich, I. Grout, Y. E. Aimine, A. Richardson, J. Contensou
{"title":"A new quality estimation methodology for mixed-signal and analogue ICs","authors":"T. Olbrich, I. Grout, Y. E. Aimine, A. Richardson, J. Contensou","doi":"10.1109/EDTC.1997.582419","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582419","url":null,"abstract":"IC product quality is commonly described as the faulty device level at shipment and is becoming an increasingly important metric in the Microelectronics Industry. This paper presents and demonstrates a quality estimation approach based on Inductive Fault Analysis for mixed-signal and analogue ICs, that quantitatively models the quality related parameters prior to production. It is shown how the approach can be used to optimise the manufacturing test program.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117184117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Library mapping for memories 内存库映射
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582372
P. Jha, N. Dutt
{"title":"Library mapping for memories","authors":"P. Jha, N. Dutt","doi":"10.1109/EDTC.1997.582372","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582372","url":null,"abstract":"We present a library mapping technique that synthesizes a source memory module from a library of target memory modules. We define the library mapping problem for memories, identify and solve the three subproblems of port, bit-width and size (word) mapping associated with this task and finally combine these solutions into an efficient memory mapping algorithm. Experimental results on a number of memory-intensive designs demonstrate that our memory mapping approach generates a wide variety of cost-effective designs, often counter-intuitive ones, based on a user-given cost function and the target library.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124644971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Retargetable generation of code selectors from HDL processor models 可从HDL处理器模型中重新生成代码选择器
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582348
R. Leupers, P. Marwedel
{"title":"Retargetable generation of code selectors from HDL processor models","authors":"R. Leupers, P. Marwedel","doi":"10.1109/EDTC.1997.582348","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582348","url":null,"abstract":"Besides high code quality, a primary issue in embedded code generation is retargetability of code generators. This paper presents techniques for automatic generation of code selectors from externally specified processor models. In contrast to previous work, our retargetable compiler RECORD does not require tool-specific modelling formalisms, but starts from general HDL processor models. From an HDL model, all processor aspects needed for code generation are automatically derived. As demonstrated by experimental results, short turnaround times for retargeting are achieved, which permits study of the HW/SW trade-off between processor architectures and program execution speed.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"384 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126731150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 75
Cellular automata for generating deterministic test sequences 用于生成确定性测试序列的元胞自动机
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582336
D. Kagaris, S. Tragoudas
{"title":"Cellular automata for generating deterministic test sequences","authors":"D. Kagaris, S. Tragoudas","doi":"10.1109/EDTC.1997.582336","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582336","url":null,"abstract":"We propose an on-chip test pattern generator that uses a one-dimensional cellular automaton (CA) to generate either a precomputed sequence of test patterns or pairs of test patterns for path delay faults. To our knowledge, this is the first approach that guarantees successful on-chip generation of a given test pattern sequence (or a given test set for path delay faults) using a finite number of CA cells. Given a pair of columns (C/sub u/,C/sub v/) of the test matrix, the proposed method uses alternative \"linking procedures\" P/sub j/ that compute the number of extra CA cells to enable the generation of (C/sub u/,C/sub v/) by the CA. A systematic approach uses the linking procedures to minimize the total number of needed CA cells. Experimental results show that the hardware overhead is often reasonable. The performance of the scheme depends on an appropriate choice of linking procedures P/sub j/.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132459988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A new field programmable system-on-a-chip for mixed signal integration 一种用于混合信号集成的新型现场可编程单片系统
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582424
J. Faura, C. Horton, B. Krah, J. Cabestany, M. Aguirre, J. Insenser
{"title":"A new field programmable system-on-a-chip for mixed signal integration","authors":"J. Faura, C. Horton, B. Krah, J. Cabestany, M. Aguirre, J. Insenser","doi":"10.1109/EDTC.1997.582424","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582424","url":null,"abstract":"A new RAM-based, mixed-signal, multicontext dynamically reconfigurable Field Programmable Device with on-chip microprocessor is described. A completely integrated mixed-signal CAD and microprocessor programming environment is used to design and simulate electronic systems composed by microprocessor code and digital and analog hardware. The very flexible communication between the microprocessor, the configurable digital cells and the programmable analog blocks makes possible powerful integration, real-time emulation (internal signals and configuration are available to the microprocessor) and advanced run-time reconfiguration.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129178674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A scheme for multiple on-chip signature checking for embedded SRAMs 嵌入式ram的多片上签名检测方案
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582438
M. F. Abdulla, C. Ravikumar, Anshul Kumar
{"title":"A scheme for multiple on-chip signature checking for embedded SRAMs","authors":"M. F. Abdulla, C. Ravikumar, Anshul Kumar","doi":"10.1109/EDTC.1997.582438","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582438","url":null,"abstract":"Pseudorandom self testing of embedded memories is commonly used because of its simplicity. A novel scheme pseudorandom testing with multiple on-chip signature checking (MOSC) has been proposed. Although this scheme results in significant reductions in aliasing probability at no significant increase in area in most cases, the test area and time overhead may be excessive if the circuit contains multiple embedded RAMs of various sizes. Example of such circuits are the ASICs for the telecommunications. In this paper, we propose a Static-RAM BIST scheme, based on the MOSC scheme, which is applicable for testing chips that have multiple embedded RAMs of various sizes.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133322310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
New static compaction techniques of test sequences for sequential circuits 时序电路测试序列的静态压缩新技术
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582327
Fulvio Corno, P. Prinetto, M. Rebaudengo, M. Reorda
{"title":"New static compaction techniques of test sequences for sequential circuits","authors":"Fulvio Corno, P. Prinetto, M. Rebaudengo, M. Reorda","doi":"10.1109/EDTC.1997.582327","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582327","url":null,"abstract":"This paper describes an algorithm for compacting the Test Sequences generated by an ATPG tool without reducing the number of faults they detect. The algorithm is based on re-ordering the sequences so that some of them can be shortened and some others eliminated. The problem is NP-complete, and we adopt Genetic Algorithms to obtain optimal solutions with acceptable computational requirements. As it requires just one preliminary Fault Simulation experiment, the approach is much more efficient than others proposed before; experimental results gathered with Test Sets generated by different ATPG tools show that the method is able to reduce the size of the Test Set by a factor varying between 50% and 62%.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"527 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133101931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书