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Proceedings European Design and Test Conference. ED & TC 97最新文献

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Procedure cloning: a transformation for improved system-level functional partitioning 过程克隆:用于改进系统级功能分区的转换
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582405
F. Vahid
{"title":"Procedure cloning: a transformation for improved system-level functional partitioning","authors":"F. Vahid","doi":"10.1109/EDTC.1997.582405","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582405","url":null,"abstract":"Functional partitioning assigns the functions of a system's program-like specification among system components, such as standard-software and custom-hardware processors. We introduce a new transformation, called procedure cloning, that significantly improves functional partitioning results. The transformation creates a clone of a procedure for sole use by a particular procedure caller, so the clone can be assigned to the caller's processor, which in turn improves performance through reduced communication. We define several cloning heuristics that seek to clone the minimum number of procedures, a goal necessary to obtain the best improvements. We highlight experiments comparing our cloning heuristics and showing partition improvements with cloning.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126640081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
PCC: a modeling technique for mixed control/data flow systems PCC:用于混合控制/数据流系统的建模技术
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582404
Thorsten Grötker, R. Schoenen, H. Meyr
{"title":"PCC: a modeling technique for mixed control/data flow systems","authors":"Thorsten Grötker, R. Schoenen, H. Meyr","doi":"10.1109/EDTC.1997.582404","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582404","url":null,"abstract":"Many signal processing systems make use of event driven mechanisms-typically based on finite state machines (FSMs)-to control the operation of the computationally intensive (data flow) parts. The state machines in turn are often fueled by external inputs as well as by feedback from the signal processing portions of the system. Packet-based transmission systems are a good example for such a close interaction between data and control flow. For a smooth design flow with a maximum degree of modularity it is of crucial importance to be able to model the complete functionality of the system, containing both control and data flow, within one single design environment. While the degree of abstraction should be sufficiently high to model and simulate efficiently, the link to implementation has to be fully supported. For these reasons we developed a computational model that integrates the specification of control and data flow. It combines the notion of multirate dynamic data flow graphs with event driven process activation. Thus, it maintains the flexibility and expressive power of data flow representations while enabling designers to efficiently control these operations by incorporating control automata that may have been designed using protocol compilers or state machine tools.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127836764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A new field programmable system-on-a-chip for mixed signal integration 一种用于混合信号集成的新型现场可编程单片系统
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582424
J. Faura, C. Horton, B. Krah, J. Cabestany, M. Aguirre, J. Insenser
{"title":"A new field programmable system-on-a-chip for mixed signal integration","authors":"J. Faura, C. Horton, B. Krah, J. Cabestany, M. Aguirre, J. Insenser","doi":"10.1109/EDTC.1997.582424","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582424","url":null,"abstract":"A new RAM-based, mixed-signal, multicontext dynamically reconfigurable Field Programmable Device with on-chip microprocessor is described. A completely integrated mixed-signal CAD and microprocessor programming environment is used to design and simulate electronic systems composed by microprocessor code and digital and analog hardware. The very flexible communication between the microprocessor, the configurable digital cells and the programmable analog blocks makes possible powerful integration, real-time emulation (internal signals and configuration are available to the microprocessor) and advanced run-time reconfiguration.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129178674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Full custom chip set for high speed serial communications up to 2.48 Gbit/s 全定制芯片组高速串行通信高达2.48 Gbit/s
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582427
J. Gonzalez‐Torres, P. Mateos, J. Hernandez
{"title":"Full custom chip set for high speed serial communications up to 2.48 Gbit/s","authors":"J. Gonzalez‐Torres, P. Mateos, J. Hernandez","doi":"10.1109/EDTC.1997.582427","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582427","url":null,"abstract":"A full custom chip set has been developed (within the ESPRIT III SPIBOC project) to perform high speed serial-parallel conversion on an optical link. It is composed by two complementary circuits for 8-bit parallel to serial multiplexing and serial to parallel demultiplexing (@2.5 Gbit/s). Each integrated circuit has four identical modules in order to optimize area on board. An aggregated bit rate of 10 Gb/s is achieved. The purpose of the multiplexer chip, called HSS (High Speed Serialiser), is to adapt incoming data from external circuits to the laser driver required to transmit the information to the optical/electrical interface. In a similar way, the demultiplexer chip, called HSD (High Speed Deserialiser), takes the serial flow of transmitted data from the receiver and converts it to the primacy 8-bit-wide parallel format.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130733085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs 一种性能驱动的放置算法，同时用于模拟ic的放置和路由优化
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582389
J. A. Prieto, A. Rueda, J. Quintana, J. Huertas
{"title":"A performance-driven placement algorithm with simultaneous Place&Route optimization for analog ICs","authors":"J. A. Prieto, A. Rueda, J. Quintana, J. Huertas","doi":"10.1109/EDTC.1997.582389","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582389","url":null,"abstract":"This paper presents a performance-driven placement algorithm for automatic layout generation of analog ICs. The main innovations of our approach are essentially: (i) an integrated Place&Route optimization algorithm which is able to provide a realistic measurement of the interconnect parasitics, that is a key issue in performance-driven approaches; and (ii) the simultaneous consideration in the cost function of two levels of symmetries: global symmetry with respect to virtual axes and local symmetry affecting groups of cells. The flexibility and efficiency of the algorithm is mainly due to the use of the same slicing-tree representation for placement and global routing, and to the heuristic algorithm we propose for the global routing estimate. The feasibility of the proposed approach has been demonstrated with several practical examples.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131086214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Cellular automata for generating deterministic test sequences 用于生成确定性测试序列的元胞自动机
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582336
D. Kagaris, S. Tragoudas
{"title":"Cellular automata for generating deterministic test sequences","authors":"D. Kagaris, S. Tragoudas","doi":"10.1109/EDTC.1997.582336","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582336","url":null,"abstract":"We propose an on-chip test pattern generator that uses a one-dimensional cellular automaton (CA) to generate either a precomputed sequence of test patterns or pairs of test patterns for path delay faults. To our knowledge, this is the first approach that guarantees successful on-chip generation of a given test pattern sequence (or a given test set for path delay faults) using a finite number of CA cells. Given a pair of columns (C/sub u/,C/sub v/) of the test matrix, the proposed method uses alternative \"linking procedures\" P/sub j/ that compute the number of extra CA cells to enable the generation of (C/sub u/,C/sub v/) by the CA. A systematic approach uses the linking procedures to minimize the total number of needed CA cells. Experimental results show that the hardware overhead is often reasonable. The performance of the scheme depends on an appropriate choice of linking procedures P/sub j/.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132459988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Analyzing testability from behavioral to RT level 分析从行为到RT级别的可测试性
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582352
M. Flottes, R. Pires, B. Rouzeyre
{"title":"Analyzing testability from behavioral to RT level","authors":"M. Flottes, R. Pires, B. Rouzeyre","doi":"10.1109/EDTC.1997.582352","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582352","url":null,"abstract":"In this paper, we present a method for analyzing the testability of a circuit during high level synthesis. The testability analysis returns values that represent the relative difficulty for computing test data, whatever the level of description of a circuit is (from the behavioral level-initial specification-down to the Register Transfer Level-high level synthesis output-). Experiments show the good correlation of the so-obtained testability measures with gate-level testability measures (e.g. Scoap). The proposed measures are used to guide high level synthesis towards the generation of easily SATPG testable datapaths.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133087061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
New static compaction techniques of test sequences for sequential circuits 时序电路测试序列的静态压缩新技术
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582327
Fulvio Corno, P. Prinetto, M. Rebaudengo, M. Reorda
{"title":"New static compaction techniques of test sequences for sequential circuits","authors":"Fulvio Corno, P. Prinetto, M. Rebaudengo, M. Reorda","doi":"10.1109/EDTC.1997.582327","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582327","url":null,"abstract":"This paper describes an algorithm for compacting the Test Sequences generated by an ATPG tool without reducing the number of faults they detect. The algorithm is based on re-ordering the sequences so that some of them can be shortened and some others eliminated. The problem is NP-complete, and we adopt Genetic Algorithms to obtain optimal solutions with acceptable computational requirements. As it requires just one preliminary Fault Simulation experiment, the approach is much more efficient than others proposed before; experimental results gathered with Test Sets generated by different ATPG tools show that the method is able to reduce the size of the Test Set by a factor varying between 50% and 62%.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"527 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133101931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
An asynchronous architecture for digital signal processors 数字信号处理器的异步架构
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582428
M. R. Karthikeyan, S. Nandy
{"title":"An asynchronous architecture for digital signal processors","authors":"M. R. Karthikeyan, S. Nandy","doi":"10.1109/EDTC.1997.582428","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582428","url":null,"abstract":"Summary form only given. We propose an asynchronous architecture for digital signal processors. This is based on a modification of the counterflow pipeline. In addition to registers, we apply the counterflow technique to memory operands as well. This results in an asynchronous architecture with good performance potential for DSP. We describe the architecture below.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"63 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133072911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A scheme for multiple on-chip signature checking for embedded SRAMs 嵌入式ram的多片上签名检测方案
Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI: 10.1109/EDTC.1997.582438
M. F. Abdulla, C. Ravikumar, Anshul Kumar
{"title":"A scheme for multiple on-chip signature checking for embedded SRAMs","authors":"M. F. Abdulla, C. Ravikumar, Anshul Kumar","doi":"10.1109/EDTC.1997.582438","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582438","url":null,"abstract":"Pseudorandom self testing of embedded memories is commonly used because of its simplicity. A novel scheme pseudorandom testing with multiple on-chip signature checking (MOSC) has been proposed. Although this scheme results in significant reductions in aliasing probability at no significant increase in area in most cases, the test area and time overhead may be excessive if the circuit contains multiple embedded RAMs of various sizes. Example of such circuits are the ASICs for the telecommunications. In this paper, we propose a Static-RAM BIST scheme, based on the MOSC scheme, which is applicable for testing chips that have multiple embedded RAMs of various sizes.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133322310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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