数字信号处理器的异步架构

Proceedings European Design and Test Conference. ED & TC 97 Pub Date : 1997-03-17 DOI:10.1109/EDTC.1997.582428

M. R. Karthikeyan, S. Nandy

{"title":"数字信号处理器的异步架构","authors":"M. R. Karthikeyan, S. Nandy","doi":"10.1109/EDTC.1997.582428","DOIUrl":null,"url":null,"abstract":"Summary form only given. We propose an asynchronous architecture for digital signal processors. This is based on a modification of the counterflow pipeline. In addition to registers, we apply the counterflow technique to memory operands as well. This results in an asynchronous architecture with good performance potential for DSP. We describe the architecture below.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"63 5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An asynchronous architecture for digital signal processors\",\"authors\":\"M. R. Karthikeyan, S. Nandy\",\"doi\":\"10.1109/EDTC.1997.582428\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Summary form only given. We propose an asynchronous architecture for digital signal processors. This is based on a modification of the counterflow pipeline. In addition to registers, we apply the counterflow technique to memory operands as well. This results in an asynchronous architecture with good performance potential for DSP. We describe the architecture below.\",\"PeriodicalId\":297301,\"journal\":{\"name\":\"Proceedings European Design and Test Conference. ED & TC 97\",\"volume\":\"63 5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-03-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings European Design and Test Conference. ED & TC 97\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDTC.1997.582428\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings European Design and Test Conference. ED & TC 97","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDTC.1997.582428","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

只提供摘要形式。我们提出了一种用于数字信号处理器的异步架构。这是基于对逆流管道的修改。除了寄存器之外，我们还将逆流技术应用于内存操作数。这为DSP提供了一个具有良好性能潜力的异步架构。我们将在下面描述该体系结构。

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An asynchronous architecture for digital signal processors

Summary form only given. We propose an asynchronous architecture for digital signal processors. This is based on a modification of the counterflow pipeline. In addition to registers, we apply the counterflow technique to memory operands as well. This results in an asynchronous architecture with good performance potential for DSP. We describe the architecture below.

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Proceedings European Design and Test Conference. ED & TC 97

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