{"title":"边界扫描架构的扩展和BIST的新思想,使互连更有效的测试和自测试","authors":"A. Kristof","doi":"10.1109/EDTC.1997.582443","DOIUrl":null,"url":null,"abstract":"The approach presented in this paper enables more effective testing of on-board and board-to-board interconnections and significantly simplifies the interconnection self-testing. Some extensions must be added to the Boundary Scan Architecture which, however, do not violate the JTAG/IEEE1149.1 standard requirements. Benefits are the reduced complexity and cost of an on-board testing unit as well as better test performance.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections\",\"authors\":\"A. Kristof\",\"doi\":\"10.1109/EDTC.1997.582443\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The approach presented in this paper enables more effective testing of on-board and board-to-board interconnections and significantly simplifies the interconnection self-testing. Some extensions must be added to the Boundary Scan Architecture which, however, do not violate the JTAG/IEEE1149.1 standard requirements. Benefits are the reduced complexity and cost of an on-board testing unit as well as better test performance.\",\"PeriodicalId\":297301,\"journal\":{\"name\":\"Proceedings European Design and Test Conference. ED & TC 97\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-03-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings European Design and Test Conference. ED & TC 97\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDTC.1997.582443\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings European Design and Test Conference. ED & TC 97","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDTC.1997.582443","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Extension of the boundary-scan architecture and new idea of BIST for more effective testing and self-testing of interconnections
The approach presented in this paper enables more effective testing of on-board and board-to-board interconnections and significantly simplifies the interconnection self-testing. Some extensions must be added to the Boundary Scan Architecture which, however, do not violate the JTAG/IEEE1149.1 standard requirements. Benefits are the reduced complexity and cost of an on-board testing unit as well as better test performance.