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2019 Devices for Integrated Circuit (DevIC)最新文献

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QCA Realization of Reversible Gates Using Layered T Logic Reduction Technique 用分层T逻辑约简技术实现可逆门的QCA
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783852
Chiradeep Mukherjee, Saradindu Panda, A. Mukhopadhyay, B. Maji
{"title":"QCA Realization of Reversible Gates Using Layered T Logic Reduction Technique","authors":"Chiradeep Mukherjee, Saradindu Panda, A. Mukhopadhyay, B. Maji","doi":"10.1109/DEVIC.2019.8783852","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783852","url":null,"abstract":"Quantum-dot cellular automata (QCA) becomes a promising model of computation as it possesses extreme-high packing density, ultra-high speed and low power dissipation for various nanoscale computing architectures. In this work, QCA based designs of Feynman, Toffoli, Fredkin and Peres gates are presented. These elementary gates are realized by utilizing layered T logic reduction technique. The QCA designs are evaluated in terms of QCA design metrics like the number of quantum cells, area, and delay. The analysis shows significant improvements over existing models in terms of QCA design metrics. As a result, the proposed layered T based QCA layouts of elementary reversible gates become an excellent candidate for developing multilevel reversible circuits.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115528512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Diode & Neutral Point Clamped Five-Level Inverter For the Power Quality Issues 用于电能质量问题的二极管和中性点箝位五电平逆变器
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783920
Rabindranath Das Adhikary, Writwik Balow, T. Halder
{"title":"Diode & Neutral Point Clamped Five-Level Inverter For the Power Quality Issues","authors":"Rabindranath Das Adhikary, Writwik Balow, T. Halder","doi":"10.1109/DEVIC.2019.8783920","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783920","url":null,"abstract":"The five-level inverter is attractive for medium power applications with reduced voltage and current stress by virtue of which lower rating of semiconductors for the medium and high voltage applications. This inverter is productive for the reduced total harmonic distortions (THD) to accomplish the good quality of the power in addition to lower size of the filter components as cost effective solution for the aggressive power market. The inverter also make certain to avoid the complications of the static and dynamic voltage sharing when the power semiconductors are connected in series with a multi-leveled-inverter topology.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"285 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114179129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Metal Grain Granularity Induced Variability in Gate-All-Around Si-Nanowire Transistors at 1nm Technology Node 金属晶粒度对栅极全能硅纳米线晶体管的影响
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783717
Tara Prasanna Dash, S. Dey, J. Jena, S. Das, E. Mohapatra, C. K. Maiti
{"title":"Metal Grain Granularity Induced Variability in Gate-All-Around Si-Nanowire Transistors at 1nm Technology Node","authors":"Tara Prasanna Dash, S. Dey, J. Jena, S. Das, E. Mohapatra, C. K. Maiti","doi":"10.1109/DEVIC.2019.8783717","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783717","url":null,"abstract":"As predicted, 5nm technology is not going to be ready for production until 2025 and it will be some sort of FinFET (possibly gate-all-around silicon nanowire or similar type of devices). It is time to search for advanced device structures such as nanowires. In this work, TCAD simulations are performed for the first time to evaluate the potential of 1nm gate length cylindrical Si channel nanowire field effect transistors (NW-FET) at extreme scaling limits. Effects of metal grain granularity (MGG) of the gate-all-around (GAA) NW-FET device have been studied to understand variability of the performance metrics such as, the threshold voltage, on-current, off-current, sub-threshold slope and drain induced barrier lowering. It is shown that the gate-all-around NW-FETs have the potential to replace FinFETs in future technology nodes because of their better channel electrostatic control.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114542616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Noise analysis of Dual Halo Dual Dielectric Triple Material Surrounding Gate MOSFET for RF applications 射频用双晕双介电三材料环栅MOSFET的噪声分析
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783796
Prashanth Kumar, N. Gupta, Rashmi Gupta, Amit Sharma
{"title":"Noise analysis of Dual Halo Dual Dielectric Triple Material Surrounding Gate MOSFET for RF applications","authors":"Prashanth Kumar, N. Gupta, Rashmi Gupta, Amit Sharma","doi":"10.1109/DEVIC.2019.8783796","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783796","url":null,"abstract":"In this paper, the noise performance of Dual Halo Dual Dielectric Triple Material Surrounding Gate (DH-DD-TM-SG) MOSFET has been investigated. The assessment of noise performance has been carried out in terms of noise figure, noise conductance and optimum impedance. These noise metrics reveal notable cutback in noise by virtue of dual dielectric and dual halo implants in DH-DD-TM-SG MOSFET in contrast to conventional Triple Material Surrounding Gate (TM-SG) MOSFET. It is scrutinized that noise figure is shrunk by 35.7% and optimum impedance is raised by 14.49% in DH-DD-TM-SG MOSFET than its counterpart, making it a suitable device for designing of low-noise amplifiers.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128420073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Low Power LNA using Current Reused Technique for UWB Application 基于电流复用技术的低功耗LNA在超宽带中的应用
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783936
Dhananjaya Tripathy, D. Nayak, S. Biswal, S. Swain, Biswajit Baral, S. K. Das
{"title":"A Low Power LNA using Current Reused Technique for UWB Application","authors":"Dhananjaya Tripathy, D. Nayak, S. Biswal, S. Swain, Biswajit Baral, S. K. Das","doi":"10.1109/DEVIC.2019.8783936","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783936","url":null,"abstract":"Here in this paper the design of a low power low noise amplifier (LNA) is presented which works for very wideband of frequency known as UWB signals. This method uses current reused technique which helps in reducing the power consumption while maintaining the same conversion gain and NF. No inductor is used in this circuit which reduces the complexity. Here a power gain of 12.6 dB, a NF of 2.1 dB at 3.5 GHz and 8.5 GHz is achieved, while consuming very less power nearly 7.6mW. It is clear from the observations that this technique solves the major problem of power consumption that was present in the previously existing techniques.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114538516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Forecasting Solar Potential Using Support Vector Regression 利用支持向量回归预测太阳能潜力
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783431
Subham Shaw, M. Prakash
{"title":"Forecasting Solar Potential Using Support Vector Regression","authors":"Subham Shaw, M. Prakash","doi":"10.1109/DEVIC.2019.8783431","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783431","url":null,"abstract":"Solar energy is one of the most commonly used renewable energy resources. To obtain reliable output from solar energy, prediction of solar radiation is necessary. In this paper, a solar radiation prediction model has been developed for New Alipore, Kolkata. Easily available meteorological parameters like temperature, pressure and humidity have been utilized as inputs, to build the prediction model. Two years data (2011–2012) have been used to develop the Support Vector Regression (SVR) based solar radiation prediction model. The results obtained from the prediction model have been validated with the help of statistical metrics, Root-Mean-Square Error (RMSE) and Coefficient of Determination $(mathrm{R}^{2})$. The results signifies that the performance of the developed model is better in comparison with the models existing in the literature.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131354476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An approach towards the development of refreshable Braille Computer Display Unit 可刷新盲文计算机显示单元的研制方法
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783582
Moumita Ghosh, Subham Ghosh, Shivam Sarkar, Kaustav Saha, Anirudha Ray, B. Neogi
{"title":"An approach towards the development of refreshable Braille Computer Display Unit","authors":"Moumita Ghosh, Subham Ghosh, Shivam Sarkar, Kaustav Saha, Anirudha Ray, B. Neogi","doi":"10.1109/DEVIC.2019.8783582","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783582","url":null,"abstract":"Modern time is the age of digitalization. People are accessing information with the advancement of digital technology. Blinds have very limited accessible resources to access this digitalized information. In this article, a novel proposal about working and development of an electronic refreshable braille display unit to build a getaway to the digital world for the blind people. An economic adoption of a tactile display having an array of six small independent vibrator motors are arranged in an array of a 3×2 matrix. The system would be enabled to initially capture information from computer screen then with suitable image processing, characters recognition and stimulation of target motor/s would enable enhanced readability of the texts.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131003048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analysis of Adiabatic flip-flops for Ultra Low Power Applications 超低功耗绝热触发器分析
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783892
S. Samanta, Rajat Mahapatra, A. K. Mal
{"title":"Analysis of Adiabatic flip-flops for Ultra Low Power Applications","authors":"S. Samanta, Rajat Mahapatra, A. K. Mal","doi":"10.1109/DEVIC.2019.8783892","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783892","url":null,"abstract":"In this paper we have presented adiabatic flip flops which are used for clocking in digital systems. The clocking scheme using energy recovery technique has already appeared as a successful and promising scheme for limiting power dissipation in ultra low power digital systems. Adiabatic flip flops are the key elements for this type of energy efficient adiabatic clocking scheme. The flip-flops are working in adiabatic principle. Here in this work we have done the simulation and analyze the performance of two basic types of energy recovery flip flops. These are single ended conditional capturing flip-flop and differential conditional capturing flip flop. Both the flip-flops are utilizing energy recovery scheme. For better comparison results we have also used clock gating scheme along with energy recovery technique. Using cadence 180nm technology the simulations are obtained.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117093490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Copyright 版权
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/devic.2019.8783490
{"title":"Copyright","authors":"","doi":"10.1109/devic.2019.8783490","DOIUrl":"https://doi.org/10.1109/devic.2019.8783490","url":null,"abstract":"","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129688675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Low Power Biopotential Amplifier based on Bulk Driven Quasi Floating Gate Technique 基于体驱动准浮门技术的低功耗生物电位放大器
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783245
Preeti Sharma, K. Sharma, H. S. Jatana, Rajnish Sharma
{"title":"A Low Power Biopotential Amplifier based on Bulk Driven Quasi Floating Gate Technique","authors":"Preeti Sharma, K. Sharma, H. S. Jatana, Rajnish Sharma","doi":"10.1109/DEVIC.2019.8783245","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783245","url":null,"abstract":"Design of low-power and low-noise Biopotential Amplifier (BPA) plays crucial role in the success of high end medical diagnosis systems. However, most of these researched BPAs face a major challenge of consuming large amount of power and also exhibit high values of Noise Efficiency Factor (NEF). Here we report the design of a BPA using Bulk-Driven Quasi-Floating Gate (BDQFG) technique which consumes only low-power $(mathbf{0.657 mu mathrm{W})}$ and also exhibits NEF of 2.06. Circuit design and simulation have been performed in Cadence Analog Design Environment using standard $mathbf{0.18 mu mathrm{m}}$ technology. Besides promising results on power and noise, design of the BPA using BDQFG technique has also been fine-tuned to achieve mid-band gain of 38.3 dB (from 2.9 Hz to −3dB frequency of 735.5 Hz) and phase margin of 80.6°.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127129962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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