Preeti Sharma, K. Sharma, H. S. Jatana, Rajnish Sharma
{"title":"A Low Power Biopotential Amplifier based on Bulk Driven Quasi Floating Gate Technique","authors":"Preeti Sharma, K. Sharma, H. S. Jatana, Rajnish Sharma","doi":"10.1109/DEVIC.2019.8783245","DOIUrl":null,"url":null,"abstract":"Design of low-power and low-noise Biopotential Amplifier (BPA) plays crucial role in the success of high end medical diagnosis systems. However, most of these researched BPAs face a major challenge of consuming large amount of power and also exhibit high values of Noise Efficiency Factor (NEF). Here we report the design of a BPA using Bulk-Driven Quasi-Floating Gate (BDQFG) technique which consumes only low-power $(\\mathbf{0.657 \\mu \\mathrm{W})}$ and also exhibits NEF of 2.06. Circuit design and simulation have been performed in Cadence Analog Design Environment using standard $\\mathbf{0.18\\ \\mu \\mathrm{m}}$ technology. Besides promising results on power and noise, design of the BPA using BDQFG technique has also been fine-tuned to achieve mid-band gain of 38.3 dB (from 2.9 Hz to −3dB frequency of 735.5 Hz) and phase margin of 80.6°.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Devices for Integrated Circuit (DevIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DEVIC.2019.8783245","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Design of low-power and low-noise Biopotential Amplifier (BPA) plays crucial role in the success of high end medical diagnosis systems. However, most of these researched BPAs face a major challenge of consuming large amount of power and also exhibit high values of Noise Efficiency Factor (NEF). Here we report the design of a BPA using Bulk-Driven Quasi-Floating Gate (BDQFG) technique which consumes only low-power $(\mathbf{0.657 \mu \mathrm{W})}$ and also exhibits NEF of 2.06. Circuit design and simulation have been performed in Cadence Analog Design Environment using standard $\mathbf{0.18\ \mu \mathrm{m}}$ technology. Besides promising results on power and noise, design of the BPA using BDQFG technique has also been fine-tuned to achieve mid-band gain of 38.3 dB (from 2.9 Hz to −3dB frequency of 735.5 Hz) and phase margin of 80.6°.