发布求助
文献互助 智能选刊 最新文献

1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers最新文献

筛选
英文 中文
A 35ns 16K NMOS static RAM 一个35ns 16K NMOS静态RAM
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/isscc.1982.1156309
K. Anami, M. Yoshimoto, H. Shinohara, Y. Hirata, H. Harada, T. Nakano
{"title":"A 35ns 16K NMOS static RAM","authors":"K. Anami, M. Yoshimoto, H. Shinohara, Y. Hirata, H. Harada, T. Nakano","doi":"10.1109/isscc.1982.1156309","DOIUrl":"https://doi.org/10.1109/isscc.1982.1156309","url":null,"abstract":"An NMOS 16K×1b static RAM optimized for low soft error sensitivity will be discussed. Access time is typically 35ns with a 275mW active power dissipation.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"XXV 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131266962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 72Kb bipolar DRAM 一个72Kb双极DRAM
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1982.1156389
R. Houghton, P. Boulay, R. Penoyer
{"title":"A 72Kb bipolar DRAM","authors":"R. Houghton, P. Boulay, R. Penoyer","doi":"10.1109/ISSCC.1982.1156389","DOIUrl":"https://doi.org/10.1109/ISSCC.1982.1156389","url":null,"abstract":"A TTL-compatible 72Kb bipolar DRAM chip (8K×9), with data stored on the junction capacitance of a 200μm2dielectric-isolation cell, will be described. The chip operates at 50ns access and 150ns cycle times.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128101868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Monolithic signal processors 单片信号处理器
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1982.1156393
C. Hewes
{"title":"Monolithic signal processors","authors":"C. Hewes","doi":"10.1109/ISSCC.1982.1156393","DOIUrl":"https://doi.org/10.1109/ISSCC.1982.1156393","url":null,"abstract":"The current state of the art in VLSI design and fabrication makes possible the implementation of processors containing array multipliers, significant amounts of memory, and other architectural features which facilitate computations required by signal processing algorithms . . . The panel will explore a number of important questions concerning the applications of these processors, their development systems and the future capabilities which ICs of this type could offer.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133637176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A linear bipolar optically-coupled isolation amplifier 一种线性双极光耦合隔离放大器
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1982.1156292
H. Skolnik
{"title":"A linear bipolar optically-coupled isolation amplifier","authors":"H. Skolnik","doi":"10.1109/ISSCC.1982.1156292","DOIUrl":"https://doi.org/10.1109/ISSCC.1982.1156292","url":null,"abstract":"A high-voltage isolation amplifier, with 0.05% nonlinearity, having greater than 160dB isolation mode rejection, will be described. Features include one LED and a pair of precision amplifiers, one with internal optical feedback for LED linearization.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132232322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A single-chip CMOS speech synthesis chip 一种单片CMOS语音合成芯片
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1982.1156315
K. Inoue, K. Wakabayashi, Y. Yoshikawa, S. Masuzawa, K. Sano, S. Kimura
{"title":"A single-chip CMOS speech synthesis chip","authors":"K. Inoue, K. Wakabayashi, Y. Yoshikawa, S. Masuzawa, K. Sano, S. Kimura","doi":"10.1109/ISSCC.1982.1156315","DOIUrl":"https://doi.org/10.1109/ISSCC.1982.1156315","url":null,"abstract":"A single chip CMOS speech synthesizer with 32Kb of speech data ROM and a D/A converter will be discussed. Design is based on a time domain algorithm that distinguishes between voiced and unvoiced utterances. The chip can produce about 35 words of high quality speech.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133276927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Numerical simulation of MOS capacitance for a wide range of temperatures, impurity profiles and surface state densities 大范围温度、杂质分布和表面态密度下MOS电容的数值模拟
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1982.1156349
R. Jaeger, S. Diehl, F. Gaensslen
{"title":"Numerical simulation of MOS capacitance for a wide range of temperatures, impurity profiles and surface state densities","authors":"R. Jaeger, S. Diehl, F. Gaensslen","doi":"10.1109/ISSCC.1982.1156349","DOIUrl":"https://doi.org/10.1109/ISSCC.1982.1156349","url":null,"abstract":"This report will describe a method for the numerical evaluation of the capacitance of MOS structures as a function of temperature for arbitrary impurity profiles and surface state distributions.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122806314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A single-chip sound synthesis microcomputer 一种单片声音合成微机
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1982.1156316
T. Oura, T. Isozaki, S. Toufuku, H. Igarashi
{"title":"A single-chip sound synthesis microcomputer","authors":"T. Oura, T. Isozaki, S. Toufuku, H. Igarashi","doi":"10.1109/ISSCC.1982.1156316","DOIUrl":"https://doi.org/10.1109/ISSCC.1982.1156316","url":null,"abstract":"The design of a single-chip NMOS sound synthesis microcomputer with a 64K ROM and 512b of RAM will be described. The device can synthesize music, imitation sounds or up to 90 seconds of a female voice, or 50 seconds of a male voice.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116782280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An NMOS DRAM controller NMOS DRAM控制器
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1982.1156398
M. Bazes, J. Nadir, D. Perlmutter, B. Mantel, O. Zak
{"title":"An NMOS DRAM controller","authors":"M. Bazes, J. Nadir, D. Perlmutter, B. Mantel, O. Zak","doi":"10.1109/ISSCC.1982.1156398","DOIUrl":"https://doi.org/10.1109/ISSCC.1982.1156398","url":null,"abstract":"An NMOS controller, generating control signals for a DRAM, with programmable interfaces, dual-port configurations and error correction support, will be discussed. The chip has a worst case delay of 35ns and can drive 500pF loads.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116846588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Differential NMOS analog building blocks for PCM telephony 用于PCM电话的差分NMOS模拟构建块
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1982.1156379
D. Senderowicz, S. Dreyer, J. Huggins, C. Rahim, C. Laber
{"title":"Differential NMOS analog building blocks for PCM telephony","authors":"D. Senderowicz, S. Dreyer, J. Huggins, C. Rahim, C. Laber","doi":"10.1109/ISSCC.1982.1156379","DOIUrl":"https://doi.org/10.1109/ISSCC.1982.1156379","url":null,"abstract":"This paper will discuss a family of differential NMOS analog circuits developed for CODEC/filter telephony applications. Switched capacitor filters, auto zero circuits, an encoder, output filter and various gain blocks, including a Power amplifier, will be described.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116200697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An automatically designed 32b CMOS VLSI processor 自动设计的32b CMOS VLSI处理器
1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI: 10.1109/ISSCC.1982.1156372
S. Horiguchi, H. Yoshimura, R. Kassai, T. Sudo
{"title":"An automatically designed 32b CMOS VLSI processor","authors":"S. Horiguchi, H. Yoshimura, R. Kassai, T. Sudo","doi":"10.1109/ISSCC.1982.1156372","DOIUrl":"https://doi.org/10.1109/ISSCC.1982.1156372","url":null,"abstract":"A 32b CMOS VLSI processor chip designed automatically, including 17K gates of random logic and 2304b RAM will be described. Silicon gate technology offers an average loaded propagation delay of 1.6ns/gate using 2μm design rules.","PeriodicalId":291836,"journal":{"name":"1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130405934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书