NMOS DRAM控制器

1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1982.1156398

M. Bazes, J. Nadir, D. Perlmutter, B. Mantel, O. Zak

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引用次数: 0

摘要

NMOS控制器，为DRAM产生控制信号，具有可编程接口，双端口配置和纠错支持，将被讨论。该芯片的最坏情况延迟为35ns，可驱动500pF负载。

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An NMOS DRAM controller

An NMOS controller, generating control signals for a DRAM, with programmable interfaces, dual-port configurations and error correction support, will be discussed. The chip has a worst case delay of 35ns and can drive 500pF loads.

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来源期刊

1982 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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