Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming最新文献

{"title":"Assertional reasoning about data races in relaxed memory models","authors":"B. Sanders, Kyunghee Kim","doi":"10.1145/1345206.1345249","DOIUrl":"https://doi.org/10.1145/1345206.1345249","url":null,"abstract":"We describe the ideas behind a method to use assertional reasoning to statically show that all sequentially consistent executions of a concurrent program are free from data races.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114969218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Nested parallelism in transactional memory","authors":"Kunal Agrawal, Jeremy T. Fineman, Jim Sukha","doi":"10.1145/1345206.1345232","DOIUrl":"https://doi.org/10.1145/1345206.1345232","url":null,"abstract":"This paper investigates adding transactions with nested parallelism and nested transactions to a dynamically multithreaded parallel programming language that generates only series-parallel programs. We describe XConflict, a data structure that facilitates conflict detection for a software transactional memory system which supports transactions with nested parallelism and unbounded nesting depth. For languages that use a Cilk-like work-stealing scheduler, XConflict answers concurrent conflict queries in O(1) time and can be maintained efficiently. In particular, for a program with T1 work and a span (or critical-path length) of T∞, the running time on p processors of the program augmented with XConflict is only O(T1/p + pT∞). Using XConflict, we describe CWSTM, a runtime-system design for software transactional memory which supports transactions with nested parallelism and unbounded nesting depth of transactions. The CWSTM design provides transactional memory with eager updates, eager conflict detection, strong atomicity, and lazy cleanup on aborts. In the restricted case when no transactions abort and there are no concurrent readers, CWSTM executes a transactional computation on p processors also in time O(T1/p + pT∞). Although this bound holds only under rather optimistic assumptions, to our knowledge, this result is the first theoretical performance bound on a TM system that supports transactions with nested parallelism which is independent of the maximum nesting depth of transactions.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116163111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization principles and application performance evaluation of a multithreaded GPU using CUDA","authors":"Shane Ryoo, Christopher I. Rodrigues, Sara S. Baghsorkhi, S. S. Stone, D. Kirk, Wen-mei W. Hwu","doi":"10.1145/1345206.1345220","DOIUrl":"https://doi.org/10.1145/1345206.1345220","url":null,"abstract":"GPUs have recently attracted the attention of many application developers as commodity data-parallel coprocessors. The newest generations of GPU architecture provide easier programmability and increased generality while maintaining the tremendous memory bandwidth and computational power of traditional GPUs. This opportunity should redirect efforts in GPGPU research from ad hoc porting of applications to establishing principles and strategies that allow efficient mapping of computation to graphics hardware. In this work we discuss the GeForce 8800 GTX processor's organization, features, and generalized optimization strategies. Key to performance on this platform is using massive multithreading to utilize the large number of cores and hide global memory latency. To achieve this, developers face the challenge of striking the right balance between each thread's resource usage and the number of simultaneously active threads. The resources to manage include the number of registers and the amount of on-chip memory used per thread, number of threads per multiprocessor, and global memory bandwidth. We also obtain increased performance by reordering accesses to off-chip memory to combine requests to the same or contiguous memory locations and apply classical optimizations to reduce the number of executed operations. We apply these strategies across a variety of applications and domains and achieve between a 10.5X to 457X speedup in kernel codes and between 1.16X to 431X total application speedup.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129669763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Matrix product on heterogeneous master-worker platforms","authors":"J. Dongarra, J. Pineau, Y. Robert, F. Vivien","doi":"10.1145/1345206.1345217","DOIUrl":"https://doi.org/10.1145/1345206.1345217","url":null,"abstract":"This paper is focused on designing efficient parallel matrix-product algorithms for heterogeneous master-worker platforms. While matrix-product is well-understood for homogeneous 2D-arrays of processors (e.g., Cannon algorithm and ScaLAPACK outer product algorithm), there are three key hypotheses that render our work original and innovative: - Centralized data. We assume that all matrix files originate from, and must be returned to, the master. The master distributes data and computations to the workers while in ScaLAPACK, input and output matrices are supposed to be equally distributed among participating resources beforehand). Typically, our approach is useful in the context of speeding up MATLAB or SCILAB clients running on a server (which acts as the master and initial repository of files). - Heterogeneous star-shaped platforms. We target fully heterogeneous platforms, where computational resources have different computing powers. Also, the workers are connected to the master by links of different capacities. This framework is realistic when deploying the application from the server, which is responsible for enrolling authorized resources. - Limited memory. As we investigate the parallelization of large problems, we cannot assume that full matrix column blocks can be stored in the worker memories and be re-used for subsequent updates (as in ScaLAPACK). We have devised efficient algorithms for resource selection (deciding which workers to enroll) and communication ordering (both for input and result messages), and we report a set of numerical experiments on a platform at our site. The experiments show that our matrix-product algorithm has smaller execution times than existing ones, while it also uses fewer resources.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130931553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Type inference for locality analysis of distributed data structures","authors":"S. Chandra, V. Saraswat, Vivek Sarkar, R. Bodík","doi":"10.1145/1345206.1345211","DOIUrl":"https://doi.org/10.1145/1345206.1345211","url":null,"abstract":"In languages with distributed heap data structures, the type system typically conveys only coarse locality information: whether a reference is local or possibly remote. Often, of interest to the optimizing compiler or the user is a more fine-grain information, such as whether two remote references point to objects in the same partition of the distributed heap. This paper proposes a dependent type system, called place types, to capture such fine-grain locality information. The type of each reference identifies the heap partition, called a place, that the reference points to. This type system is expressive enough to statically type several commonly used distributed data structures. It also accommodates a \"dynamic\" type when no suitable static type exists. We show how to embed this type system as type annotations in the X10 programming language. We also present a type inference algorithm for saving programmers from the burden of inserting type annotations. The type inference has been inspired by the use of type inference in functional programming languages such as ML. We have implemented the type inference algorithm in the X10 compiler. Experiments with small programs, but with the full set the relevant language features, have been successful in automatically finding the expected place types in these programs.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130305898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","authors":"S. Chatterjee, M. Scott","doi":"10.1145/1345206","DOIUrl":"https://doi.org/10.1145/1345206","url":null,"abstract":"It is our great pleasure to welcome you to PPoPP'08: The 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming. Since its inception (as PPEALS) in 1988, PPoPP has provided a leading forum for work in all aspects of parallelism and concurrency, including theoretical foundations, programming models, algorithms, applications, and systems software. Never in the past 20 years, however, has the conference been as broadly relevant as it is today: with the move to ubiquitous multicore processors and heterogeneous systems-on-chip now well underway, parallelism has moved onto the critical path of almost every development effort. \u0000 \u0000This year's call for papers attracted 102 submissions, a dramatic increase from last year's 65. Every paper was read by at least three members of the program committee; additional, outside reviews were solicited in special cases. At an in-person meeting of the program committee in October 2007, 25 papers were selected for presentation at the conference, on topics ranging from the theoretical (formal models, static analysis) to the highly applied (algorithms for special-purpose platforms). Transactional memory was the single most popular topic: the large number of acceptances in this area reflects an even larger number of very high quality submissions. Authors of high quality papers that could not be accepted for the conference proper were invited to present their work as posters. 13 of them accepted this invitation; 4 others were chosen from among 7 papers submitted explicitly as posters. \u0000 \u0000Given the significance of parallel hardware trends, the steering committee chose this year to co-locate with the International Symposium on High-Performance Computer Architecture. We are delighted to share with HPCA'08 not only the conference venue, but a much-anticipated keynote by IBM Fellow Emerita Frances Allen, parallel compiler pioneer and recipient of the 2007 ACM Turing Award. The PPoPP program also includes a panel on highly parallel programming models, moderated by John Mellor-Crummey, last year's Program Chair. Continuing a tradition begun on John's watch, the conference will be followed by a day of workshops and tutorials, among them the 3rd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT 2008).","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134125096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Session details: Keynote","authors":"Thomas Ayers","doi":"10.1145/3264844.3284809","DOIUrl":"https://doi.org/10.1145/3264844.3284809","url":null,"abstract":"","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132325535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Practical experiences with Java software transactional memory","authors":"E. Brevnov, Yuri G. Dolgov, Boris Kuznetsov, Dmitry Yershov, Vyacheslav Shakin, Dong-yuan Chen, Vijay Menon, S. Srinivas","doi":"10.1145/1345206.1345259","DOIUrl":"https://doi.org/10.1145/1345206.1345259","url":null,"abstract":"In this paper, we evaluate the emerging Transactional Memory (TM) area by developing a set of Java transactional memory workloads and studying their performance under a Java Software Transactional Memory (STM) system and comparing them to their lock based counterparts. We provide a detailed performance and memory consumption analysis of the overheads of software transactional memory and transactional workloads within a production quality open source Java Runtime system. Additionally, we detail the impact of the various performance optimizations in both workloads and the underlying runtime system to improving both single thread performance and scalability.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122535883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Formal specification of the MPI-2.0 standard in TLA+","authors":"Guodong Li, Michael Delisi, G. Gopalakrishnan, R. Kirby","doi":"10.1145/1345206.1345257","DOIUrl":"https://doi.org/10.1145/1345206.1345257","url":null,"abstract":"Parallel programs will increasingly be written using complex APIs such as MPI-2.0 [1], OpenMP [2], PThreads, etc. It is well documented that even experienced programmers misunderstand these APIs, especially when they are described in natural languages. The behavior of APIs observed through ad hoc experiments on actual platforms is not a conclusive or comprehensive description of the standard. Formal specifications, as currently written and distributed, are inaccessible to most practitioners. In our previous work [4], we presented the formal specification of around 30% of the MPI-1.0 primitives (mainly for point-to-point communication) in TLA+ [6]. TLA+ enjoys wide usage within (at least) Microsoft and Intel by engineers (e.g., [5]). To make our specification accessible to practitioners, we built a C front-end in the Microsoft Visual Studio (VS) parallel debugger environment through which users can submit short (perhaps tricky) MPI programs with embedded assertions, called litmus tests. This input is turned into TLA+ code and run through the TLC model checker [6]. This permits practitioners to play with (and find holes in) the semantics. We also maintain cross-reference tags with the MPI reference document for traceability. While we have demonstrated the merits of our previous work ([4]), this paper handles far more details including those pertaining to data transfers. In this work, we have covered much of MPI-2.0 (has over 300 API functions, as opposed to 128 for MPI-1.0). In addition, our new work provides a rich collection of tests that help validate our specifications. It also modularizes the specification, permitting reuse. The approximate sizes (without including comments and blank lines) of the major parts in the current TLA+ specification are shown in Table 1. We do not plan to model primitives whose behavior depends on the underlying operating system, The framework plus our TLA+ models can be downloaded from [3]. In [4], we describe an execution environment into which users can supply litmus tests and calculate their outcomes directly based","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131109533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Concurrent GC leveraging transactional memory","authors":"Phil McGachey, Ali-Reza Adl-Tabatabai, Richard L. Hudson, Vijay Menon, Bratin Saha, T. Shpeisman","doi":"10.1145/1345206.1345238","DOIUrl":"https://doi.org/10.1145/1345206.1345238","url":null,"abstract":"We predict that the ever-growing number of cores on our desktops will require a re-examination of concurrent programming. Two technologies are likely to become mainstream in response: Transactional memory provides a superior programming model to traditional lock-based concurrency, while Concurrent GC can take advantage of multiple cores to eliminate perceptible pauses in desktop applications such as games or Internet telephony. This paper proposes a combination of the two technologies, producing a synergy that improves scalability while eliminating the annoyance of user-perceivable pauses. Specifically, we show how concurrent GC can share some of the mechanisms required for transactional memory. Thus as transactional memory becomes more efficient, so too will concurrent GC. We demonstrate how, using a state of the art software transactional memory system, we can build a state of the art concurrent collector. Our goal was to reduce 90% of pause times to under one millisecond. Of the remainder, we aim for 90% to be under 10ms, and90% of those left to be under 100ms. Our performance results show that we were able to achieve these targets, with pause times between one or two orders of magnitude lower than mainstream technologies.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124500729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}