{"title":"Probabilistic advanced reservations for batch-scheduled parallel machines","authors":"Daniel Nurmi, R. Wolski, J. Brevik","doi":"10.1145/1345206.1345260","DOIUrl":"https://doi.org/10.1145/1345206.1345260","url":null,"abstract":"In high-performance computing (HPC) settings, in which multiprocessor machines are shared among users with potentially competing resource demands, processors are allocated to user workload using space sharing. Typically, users interact with a given machine by submitting their jobs to a centralized batch scheduler that implements a site-specific, and often partially hidden, policy designed to maximize machine utilization while providing tolerable turn-around times. In practice, while most HPC systems experience good utilization levels, the amount of time experienced by individual jobs waiting to begin execution has been shown to be highly variable and difficult to predict, leading to user confusion and/or frustration. One method for dealing with this uncertainty that has been proposed is to allow users who are willing to plan ahead to make “advanced reservations” for processor resources. To date, however, few if any HPC centers provide an advanced reservation capability to their general user populations for fear (supported by previous research) that diminished machine utilization will occur if and when advanced reservations are introduced. In this work, we describe VARQ, a new method for job scheduling that provides users with probabilistic “virtual” advanced reservations using only existing best effort batch schedulers and policies. VARQ functions as an overlay, submitting jobs that are indistinguishable from the normal workload serviced by a scheduler. We describe the statistical methods we use to implement VARQ, detail an empirical evaluation of its effectiveness in a number of HPC settings, and explore the potential future impact of VARQ should it become widely used. Without requiring HPC sites to support advanced reservations, we find that VARQ can implement a reservation capability probabilistically and that the effects of this probabilistic approach are unlikely to negatively affect resource utilization.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122160889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jeff Diamond, Behnam Robatmili, S. Keckler, R. V. D. Geijn, Kazushige Goto, D. Burger
{"title":"High performance dense linear algebra on a spatially distributed processor","authors":"Jeff Diamond, Behnam Robatmili, S. Keckler, R. V. D. Geijn, Kazushige Goto, D. Burger","doi":"10.1145/1345206.1345218","DOIUrl":"https://doi.org/10.1145/1345206.1345218","url":null,"abstract":"As technology trends have limited the performance scaling of conventional processors, industry and academic research has turned to parallel architectures on a single chip, including distributed uniprocessors and multicore chips. This paper examines how to extend the archtypical operation of dense linear algebra, matrix multiply, to an emerging class of uniprocessor architectures characterized by a large number of independent functional units, register banks, and cache banks connected by a 2-D on-chip network. We extend the well known algorithm for matrix multiplication by Goto to this spatially distributed class of uniprocessor and describe the optimizations of the innermost kernel, a systolic-like algorithm running on a general purpose uniprocessor. The resulting implementation yields the first demonstration of high-performance in an application executing on the TRIPS processor hardware, a next-generation distributed processor core. We show that such processors are indeed capable of substantial improvements in single threaded performance provided their spatial topography is taken into account.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131767615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Compiler optimizations for parallelizing general-purpose applications under thread-level speculation","authors":"Antonia Zhai, Shengyue Wang, P. Yew, Guojin He","doi":"10.1145/1345206.1345251","DOIUrl":"https://doi.org/10.1145/1345206.1345251","url":null,"abstract":"As technology advances, microprocessors that integrate multiple cores on a single chip are becoming increasingly common. However, extracting independent threads for parallel execution is an extremely challenging task. Thread-Level Speculation (TLS) (4; 1; 2; 3; 5) provides hardware mechanisms necessary for optimistically parallelizing potentially dependent threads. However, the ubiquitous existence of complex, input-dependent control and data dependence patterns in general-purpose applications requires a collection of compiler optimizations that target a variety of code patterns to generate efficient parallel threads. In this paper, we propose, implement and evaluate three optimization techniques to improve TLS performance.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129118287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A case study in SIMD text processing with parallel bit streams: UTF-8 to UTF-16 transcoding","authors":"R. Cameron","doi":"10.1145/1345206.1345222","DOIUrl":"https://doi.org/10.1145/1345206.1345222","url":null,"abstract":"High performance SIMD text processing using the method of parallel bit streams is introduced with a case study of UTF-8 to UTF-16 transcoding. A forward transform converts byte-oriented character stream data into eight parallel bit streams. Decoding, validation and computation of UTF-8 indexed UTF-16 bit streams are performed using bit-parallel logic and shifting operations. Conversion from UTF-8 indexing to UTF-16 indexing is performed using parallel bit deletion. The inverse transform is applied to yield high and low UTF-16 byte streams which are then merged. Combined with optimization techniques for blocks of ASCII data, speed-ups of 3 to 25 times are achieved on commodity processors compared with optimized byte-at-a-time code. Further applications of the method of parallel bit streams to bulk text processing applications are briefly discussed along with future prospects for the combination of intraregister and intrachip parallelism on multicore processors.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126793853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}