Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming最新文献_第4页

Performance without pain = productivity: data layout and collective communication in UPC 无痛苦的性能=生产力:UPC中的数据布局和集体通信

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345224

R. Nishtala, G. Almási, Calin Cascaval

{"title":"Performance without pain = productivity: data layout and collective communication in UPC","authors":"R. Nishtala, G. Almási, Calin Cascaval","doi":"10.1145/1345206.1345224","DOIUrl":"https://doi.org/10.1145/1345206.1345224","url":null,"abstract":"The next generations of supercomputers are projected to have hundreds of thousands of processors. However, as the numbers of processors grow, the scalability of applications will be the dominant challenge. This forces us to reexamine some of our fundamental ways that we approach the design and use of parallel languages and runtime systems. In this paper we show how the globally shared arrays in a popular Partitioned Global Address Space (PGAS) language, Unified Parallel C (UPC), can be combined with a new collective interface to improve both performance and scalability. This interface allows subsets, or teams, of threads to perform a collective together. As opposed to MPI's communicators, our interface allows set of threads to be placed in teams instantly rather than explicitly constructing communicators, thus allowing for a more dynamic team construction and manipulation. We motivate our ideas with three application kernels: Dense Matrix Multiplication, Dense Cholesky factorization and multidimensional Fourier transforms. We describe how the three aforementioned applications can be succinctly written in UPC thereby aiding productivity. We also show how such an interface allows for scalability by running on up to 16,384 processors on the Blue-Gene/L. In a few lines of UPC code, we wrote a dense matrix multiply routine achieves 28.8 TFlop/s and a 3D FFT that achieves 2.1 TFlop/s. We analyze our performance results through models and show that the machine resources rather than the interfaces themselves limit the performance.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127994380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 37

Where will all the threads come from? 所有的线程将从哪里来?

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345244

J. Mellor-Crummey

{"title":"Where will all the threads come from?","authors":"J. Mellor-Crummey","doi":"10.1145/1345206.1345244","DOIUrl":"https://doi.org/10.1145/1345206.1345244","url":null,"abstract":"Today, multicore microprocessors are at the heart of systems ranging from laptops to supercomputers. The shift to multicore architectures has transformed the problem of improving program performance from a micro-architecture problem to a software problem, shifting the focus from instruction-level parallelism to thread-level parallelism. As the density of transistors on chips increases, technology roadmaps call for increasing the number of cores. A key challenge facing the community is how we will keep increasing numbers of cores busy with productive work. Of great interest are answers to the question, \"Where will all the threads come from\" This panel will explore several dimensions of the problem of developing applications that effectively use extensive thread-level parallelism. First, we will hear about an initiative that aims to exploit the growing number of cores by increasing the sophistication of applications that run on the desktop. Next, we will hear about experiences mapping applications to systems with large-scale multithreading using programming models that rely on implicit and/or explicit parallelism. Finally, we will hear about past and present work on languages and compiler technology for mapping programs onto parallel systems. An aim of the panel is to identify promising directions for the future and potential stumbling blocks. The panelists have a broad range of experience with parallel applications, programming models and languages, and compiler technology for mapping languages to parallel architectures.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129659720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

ISP: a tool for model checking MPI programs 一个工具，用于模型检查MPI程序

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345258

S. Vakkalanka, Subodh Sharma, G. Gopalakrishnan, R. Kirby

{"title":"ISP: a tool for model checking MPI programs","authors":"S. Vakkalanka, Subodh Sharma, G. Gopalakrishnan, R. Kirby","doi":"10.1145/1345206.1345258","DOIUrl":"https://doi.org/10.1145/1345206.1345258","url":null,"abstract":"A significant body of parallel programs are written using MPI [1]. Bugs in MPI programs arise due to many reasons, for example: (i) during manual optimizations that turn blocking sends/receives into their non-blocking counterparts, (ii) in the context of using wild-card communications (and the resulting non-determinism), and (iii) in programs that use one-sided communication [2]. Programmers are acutely aware of the need to test parallel programs over all their interleavings. They also known that this is impossible, thus confining testing to interleavings that are guessed to be adequate – very often incorrectly, as it turns out. Model checking [4] has helped debug many concurrent systems by relying on an exhaustive search of all possible interleavings – albeit on a suitably abstracted system model. For example, SPIN [5] recently won ACM’s prestigious software award, and has been used to verify many real-world protocols. For model checking to be successful in practice: (i) Designers must have modestly expensive techniques to create models of the protocols to be verified. (ii) They must be able to examine a fraction of the interleavings in a concurrent system, and be able to claim that the remaining interleavings are equivalent and hence need not be examined, using a suitable state space reduction algorithm [4, 5]. This paper presents a tool called ISP (in-situ partial order) which aspires to grow into a practical MPI model checker. In the only other active research effort on developing a model checker (called MPI SPIN) for MPI programs [6], the following approach is taken: (i) they model MPI library functions in Promela (SPIN’s modeling language), and uses SPIN for verification; (ii) they use the C extension features of SPIN to model advanced features such as non-blocking communication commands. (iii) they require users to manually express their intended MPI C program in MPI SPIN","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"301 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121460749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 91

Session details: Keynote 会议详情:

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/3255504

S. Chatterjee

引用次数: 0

Enhancing the performance of MPI-IO applications by overlapping I/O, computation and communication 通过I/O、计算和通信的重叠来提高MPI-IO应用程序的性能

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345254

C. Patrick, S. Son, M. Kandemir

{"title":"Enhancing the performance of MPI-IO applications by overlapping I/O, computation and communication","authors":"C. Patrick, S. Son, M. Kandemir","doi":"10.1145/1345206.1345254","DOIUrl":"https://doi.org/10.1145/1345206.1345254","url":null,"abstract":"Many scientific applications process significant amounts of diskresident data. In particular, recently, applications in science, engineering, in-situ processing and others have grown by orders of magnitude in complexity, scale and the dataset sizes that they produce, manipulate, and consume. While memory capacities of parallel machines are continuously increasing, storage requirements of parallel applications that use these machines are increasing at a much faster rate. As a result, storage system performance is continuing to be one of the most important factors in determining overall application performance[3]. Many parallel I/O operations, including collective I/O, involve both disk I/O and interprocessor communication. In addition, in many I/O-intensive applications, parallel I/O operations are usually followed by parallel computations. While in a large-scale parallel application I/O, communication and computation are individually performed in parallel by multiple processors, they are not usually overlapped with each other. This paper studies several techniques that can be used for overlapping I/O, computation and communication in parallel scientific applications written using MPI and MPI-IO[4]. Our specific focus is on collective I/O operations that are followed by parallel computations. Targeting this, we present and experimentally evaluate the following overlap strategies: 1) Overlapping I/O and communication; 2) Overlapping I/O and computation; 3) Overlapping computation and communication; and 4) Overlapping I/O, communication, and computation. We tested the effectiveness of these schemes using a generic collective read operation and an out-of-core benchmark: MxM (matrix multiplication). Our experimental results show that all these techniques are effective, and bring performance improvements, ranging from 6% to 92%, using different buffer sizes and different number of processors.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129877218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

A portable runtime interface for multi-level memory hierarchies 用于多级内存层次结构的可移植运行时接口

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345229

M. Houston, Ji Young Park, Manman Ren, T. Knight, K. Fatahalian, A. Aiken, W. Dally, P. Hanrahan

引用次数: 40

Session details: Transactional memory II: STM implementation 会话细节:事务内存II: STM实现

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/3255510

Bratin Saha

引用次数: 0

Automated application-level checkpointing based on live-variable analysis in MPI programs 基于MPI程序中活变量分析的自动应用程序级检查点

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345252

Panfeng Wang, Xuejun Yang, Hongyi Fu, Yunfei Du, Zhiyun Wang, Jia Jia

引用次数: 4

Modeling optimistic concurrency using quantitative dependence analysis 使用定量依赖分析建模乐观并发性

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345234

C. V. Praun, R. Bordawekar, Calin Cascaval

{"title":"Modeling optimistic concurrency using quantitative dependence analysis","authors":"C. V. Praun, R. Bordawekar, Calin Cascaval","doi":"10.1145/1345206.1345234","DOIUrl":"https://doi.org/10.1145/1345206.1345234","url":null,"abstract":"This work presents a quantitative approach to analyze parallelization opportunities in programs with irregular memory access where potential data dependencies mask available parallelism. The model captures data and causal dependencies among critical sections as algorithmic properties and quantifies them as a density computed over the number of executed instructions. The model abstracts from runtime aspects such as scheduling, the number of threads, and concurrency control used in a particular parallelization. We illustrate the model on several applications requiring ordered and unordered execution of critical sections. We describe a run-time tool that computes the dependence densities from a deterministic single-threaded program execution. This density metric provides insights into the potential for optimistic parallelization, opportunities for algorithmic scheduling, and performance defects due to synchronization bottlenecks. Based on the results of our analysis, we classify applications into three categories with low, medium, and high dependence densities. Applications with low dependence density are naturally good candidates for optimistic concurrency, applications with medium density may require a scheduler that is aware of the algorithmic dependencies for optimistic concurrency to be effective, and applications with high dependence density may not be suitable for parallelization.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121837045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 63

Dynamic performance tuning of word-based software transactional memory 基于字的软件事务性内存的动态性能调优

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345241

P. Felber, C. Fetzer, T. Riegel

引用次数: 510