Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming最新文献_第3页

Session details: Parallel algorithms 会话详细信息:并行算法

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/3255506

G. Bronevetsky

引用次数: 0

SuperMatrix: a multithreaded runtime scheduling system for algorithms-by-blocks SuperMatrix:一个基于算法块的多线程运行时调度系统

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345227

E. Chan, F. V. Zee, P. Bientinesi, E. S. Quintana‐Ortí, G. Quintana-Ortí, R. V. D. Geijn

{"title":"SuperMatrix: a multithreaded runtime scheduling system for algorithms-by-blocks","authors":"E. Chan, F. V. Zee, P. Bientinesi, E. S. Quintana‐Ortí, G. Quintana-Ortí, R. V. D. Geijn","doi":"10.1145/1345206.1345227","DOIUrl":"https://doi.org/10.1145/1345206.1345227","url":null,"abstract":"This paper describes SuperMatrix, a runtime system that parallelizes matrix operations for SMP and/or multi-core architectures. We use this system to demonstrate how code described at a high level of abstraction can achieve high performance on such architectures while completely hiding the parallelism from the library programmer. The key insight entails viewing matrices hierarchically, consisting of blocks that serve as units of data where operations over those blocks are treated as units of computation. The implementation transparently enqueues the required operations, internally tracking dependencies, and then executes the operations utilizing out-of-order execution techniques inspired by superscalar microarchitectures. This separation of concerns allows library developers to implement algorithms without concerning themselves with the parallelization aspect of the problem. Different heuristics for scheduling operations can be implemented in the runtime system independent of the code that enqueues the operations. Results gathered on a 16 CPU ccNUMA Itanium2 server demonstrate excellent performance.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115418454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 116

Transactional boosting: a methodology for highly-concurrent transactional objects 事务性提升:一种用于高并发事务性对象的方法

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345237

M. Herlihy, Eric Koskinen

引用次数: 296

Scalable packet classification using interpreting: a cross-platform multi-core solution 使用解释的可扩展数据包分类:跨平台多核解决方案

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345214

Haipeng Cheng, Zheng Chen, Bei Hua, Xinan Tang

{"title":"Scalable packet classification using interpreting: a cross-platform multi-core solution","authors":"Haipeng Cheng, Zheng Chen, Bei Hua, Xinan Tang","doi":"10.1145/1345206.1345214","DOIUrl":"https://doi.org/10.1145/1345206.1345214","url":null,"abstract":"Packet classification is an enabling technology to support advanced Internet services. It is still a challenge for a software solution to achieve 10Gbps (line-rate) classification speed. This paper presents a classification algorithm that can be efficiently implemented on a multi-core architecture with or without cache. The algorithm embraces the holistic notion of exploiting application characteristics, considering the capabilities of the CPU and the memory hierarchy, and performing appropriate data partitioning. The classification algorithm adopts two stages: searching on a reduction tree and searching on a list of ranges. This decision is made based on a classification heuristic: the size of the range list is limited after the first stage search. Optimizations are then designed to speed up the two-stage execution. To exploit the speed gap (1) between the CPU and external memory; (2) between internal memory (cache) and external memory, an interpreter is used to trade the CPU idle cycles with demanding memory access requirements. By applying the CISC style of instruction encoding to compress the range expressions, it not only significantly reduces the total memory requirement but also makes effective use of the internal memory (cache) bandwidth. We show that compressing data structures is an effective optimization across the multi-core architectures. We implement this algorithm on both Intel IXP2800 network processor and Core 2 Duo X86 architecture, and experiment with the classification benchmark, ClassBench. By incorporating architecture-awareness in algorithm design and taking into account the memory hierarchy, data partitioning, and latency hiding in algorithm implementation, the resulting algorithm shows a good scalability on Intel IXP2800. By effectively using the cache system, the algorithm also runs faster than the previous fastest RFC on the Core 2 Duo architecture.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123675915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Semantics-based distributed I/O for mpiBLAST 基于语义的mpiBLAST分布式I/O

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345262

P. Balaji, Wu-chun Feng, J. Archuleta, Heshan Lin, R. Kettimuthu, R. Thakur, Xiaosong Ma

{"title":"Semantics-based distributed I/O for mpiBLAST","authors":"P. Balaji, Wu-chun Feng, J. Archuleta, Heshan Lin, R. Kettimuthu, R. Thakur, Xiaosong Ma","doi":"10.1145/1345206.1345262","DOIUrl":"https://doi.org/10.1145/1345206.1345262","url":null,"abstract":"BLAST is a widely used software toolkit for genomic sequence search. mpiBLAST is a freely available, open-source parallelization of BLAST that uses database segmentation to allow different worker processes to search (in parallel) unique segments of the database. After searching, the workers write their output to a filesystem. While mpiBLAST has been shown to achieve high performance in clusters with fast local filesystems, its I/O processing remains a concern for scalability, especially in systems having limited I/O capabilities such as distributed filesystems spread across a wide-area network. Thus, we present ParaMEDIC---a novel environment that uses application-specific semantic information to compress I/O data and improve performance in distributed environments. Specifically, for mpiBLAST, ParaMEDIC partitions worker processes into compute and I/O workers. Compute workers, instead of directly writing the output to the filesystem, the workers process the output using semantic knowledge about the application to generate metadata and write the metadata to the filesystem. I/O workers, which physically reside closer to the actual storage, then process this metadata to re-create the actual output and write it to the filesystem. This approach allows ParaMEDIC to reduce I/O time, thus accelerating mpiBLAST by as much as 25-fold.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121933087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

On the correctness of transactional memory 事务性内存的正确性

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345233

R. Guerraoui, M. Kapalka

{"title":"On the correctness of transactional memory","authors":"R. Guerraoui, M. Kapalka","doi":"10.1145/1345206.1345233","DOIUrl":"https://doi.org/10.1145/1345206.1345233","url":null,"abstract":"Transactional memory (TM) is perceived as an appealing alternative to critical sections for general purpose concurrent programming. Despite the large amount of recent work on TM implementations, however, very little effort has been devoted to precisely defining what guarantees these implementations should provide. A formal description of such guarantees is necessary in order to check the correctness of TM systems, as well as to establish TM optimality results and inherent trade-offs. This paper presents opacity, a candidate correctness criterion for TM implementations. We define opacity as a property of concurrent transaction histories and give its graph theoretical interpretation. Opacity captures precisely the correctness requirements that have been intuitively described by many TM designers. Most TM systems we know of do ensure opacity. At a very first approximation, opacity can be viewed as an extension of the classical database serializability property with the additional requirement that even non-committed transactions are prevented from accessing inconsistent states. Capturing this requirement precisely, in the context of general objects, and without precluding pragmatic strategies that are often used by modern TM implementations, such as versioning, invisible reads, lazy updates, and open nesting, is not trivial. As a use case of opacity, we prove the first lower bound on the complexity of TM implementations. Basically, we show that every single-version TM system that uses invisible reads and does not abort non-conflicting transactions requires, in the worst case, ?(k) steps for an operation to terminate, where k is the total number of objects shared by transactions. This (tight) bound precisely captures an inherent trade-off in the design of TM systems. The bound also highlights a fundamental gap between systems in which transactions can be fully isolated from the outside environment, e.g., databases or certain specialized transactional languages, and systems that lack such isolation capabilities, e.g., general TM frameworks.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125507516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 501

Toward high performance nonblocking software transactional memory 迈向高性能非阻塞软件事务性内存

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345240

Virendra J. Marathe, Mark Moir

{"title":"Toward high performance nonblocking software transactional memory","authors":"Virendra J. Marathe, Mark Moir","doi":"10.1145/1345206.1345240","DOIUrl":"https://doi.org/10.1145/1345206.1345240","url":null,"abstract":"Substantial advances in STM performance in recent years have mostly focused on blocking systems. We describe our work integrating the most important techniques and optimizations emerging from the recent work on blocking STMs into several variants of a nonblocking STM. In particular, our design is based on the philosophy of keeping the common, contention free execution path as simple (consequently fast) as possible, while resorting to the more expensive data displacement and metadata management only in situations where transactions have problems making forward progress. We employ novel ownership \"stealing\" and metadata management techniques in our nonblocking STM to enable several recent blocking STM optimizations such as timestamp-based validation and ownership release via store instructions, all leading to a more streamlined and efficient fast path. We present an undo log (eager versioning) variant of our STM, as well as two redo log (lazy versioning) variants, the latter of which are based on the two ownership acquisition techniques (namely eager and lazy) for writes made by transactions. Experimental results show that our efforts have improved the performance of nonblocking STMs up to the level of being competitive with the state-of-the-art blocking STMs such as TL2.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"996 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123100238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 57

Split hardware transactions: true nesting of transactions using best-effort hardware transactional memory 分割硬件事务:使用尽力而为的硬件事务内存对事务进行真正的嵌套

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345236

Yossi Lev, Jan-Willem Maessen

引用次数: 45

Session details: Runtime systems 会话详细信息:运行时系统

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/3255511

L. Iftode

引用次数: 0

Design and implementation of a high-performance MPI for C# and the common language infrastructure 基于c#和公共语言基础结构的高性能MPI的设计与实现

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345228

Douglas P. Gregor, A. Lumsdaine

{"title":"Design and implementation of a high-performance MPI for C# and the common language infrastructure","authors":"Douglas P. Gregor, A. Lumsdaine","doi":"10.1145/1345206.1345228","DOIUrl":"https://doi.org/10.1145/1345206.1345228","url":null,"abstract":"As high-performance computing enters the mainstream, parallel programming mechanisms (including the Message Passing Interface, or MPI) must be supported in new environments such as C# and the Common Language Infrastructure (CLI). Making effective use of MPI with the CLI requires an interface that reflects the high-level object-oriented nature of C# and that also supports its programming idioms. However, for performance reasons, this high-level functionality must ultimately be mapped to low-level native MPI libraries. In addition to abstraction penalty concerns, avoiding unwanted overhead in this mapping process is significantly complicated by the safety and portability features of the CLI virtual machine, such as garbage collection and just-in-time compilation. In this paper, we describe our approach to using features of C# and the CLI---such as reflection, unsafe code regions, and run-time code generation---to realize an elegant, yet highly efficient, C# interface to MPI. Experimental results demonstrate that there is no appreciable overhead introduced by our approach when compared to the native MS-MPI library.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132235817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 37