Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming最新文献_第2页

Session details: Transactional memory I 会话细节:事务内存

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/3255513

Maged M. Michael

引用次数: 0

Massive parallel LDPC decoding on GPU 大规模并行LDPC解码GPU

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345221

G. F. P. Fernandes, L. Sousa, V. Silva

引用次数: 63

Extracting coarse-grain parallelism in general-purpose programs 通用程序中粗粒度并行性的提取

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345256

S. Rul, H. Vandierendonck, K. D. Bosschere

引用次数: 12

Programming with tiles 使用tile进行编程

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345225

Jiayang Guo, Ganesh Bikshandi, B. Fraguela, M. Garzarán, D. Padua

{"title":"Programming with tiles","authors":"Jiayang Guo, Ganesh Bikshandi, B. Fraguela, M. Garzarán, D. Padua","doi":"10.1145/1345206.1345225","DOIUrl":"https://doi.org/10.1145/1345206.1345225","url":null,"abstract":"The importance of tiles or blocks in scientific computing cannot be overstated. Many algorithms, both iterative and recursive, can be expressed naturally if tiles are represented explicitly. From the point of view of performance, tiling, either as a code or a data layout transformation, is one of the most effective ways to exploit locality, which is a must to achieve good performance in current computers because of the significant difference in speed between processor and memory. Furthermore, tiles are also useful to express data distribution in parallel computations. However, despite the importance of tiles, most languages do not support them directly. This gives place to bloated programs populated with numerous subscript expressions which make the code difficult to read and coding mistakes more likely. This paper discusses Hierarchically Tiled Arrays (HTAs), a data type which facilitates the easy manipulation of tiles in object-oriented languages with emphasis on two new features, dynamic partitioning and overlapped tiling. These features facilitate the expression of locality and communication while maintaining the same performance of algorithms written using conventional languages.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"55 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120982694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 45

Safer open-nested transactions through ownership 通过所有权实现更安全的开放嵌套交易

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345261

Kunal Agrawal, I. Lee, Jim Sukha

{"title":"Safer open-nested transactions through ownership","authors":"Kunal Agrawal, I. Lee, Jim Sukha","doi":"10.1145/1345206.1345261","DOIUrl":"https://doi.org/10.1145/1345206.1345261","url":null,"abstract":"Researchers in transactional memory (TM) have proposed open nesting as a methodology for increasing the concurrency of transactional programs. The idea is to ignore ``low-level'' memory operations of an open-nested transaction when detecting conflicts for its parent transaction, and instead perform abstract concurrency control for the ``high-level'' operation that the nested transaction represents. To support this methodology, TM systems use an open-nested commit mechanism that commits all changes performed by an open-nested transaction directly to memory, thereby avoiding low-level conflicts. Unfortunately, because the TM runtime is unaware of the different levels of memory, unconstrained use of open-nested commits can lead to anomalous program behavior. We describe the framework of ownership-aware transactional memory which incorporates the notion of modules into the TM system and requires that transactions and data be associated with specific transactional modules or Xmodules. We propose a new ownership-aware commit mechanism, a hybrid between an open-nested and closed-nested commit which commits a piece of data differently depending on which Xmodule owns the data. Moreover, we provide a set of precise constraints on interactions and sharing of data among the Xmodules based on familiar notions of abstraction. The ownership-aware commit mechanism and these restrictions on Xmodules allow us to prove that ownership-aware TM has clean memory-level semantics. In particular, it guarantees serializability by modules, an adaptation of the definition of multilevel serializability from database systems. In addition, we describe how a programmer can specify Xmodules and ownership in a Java-like language. Our type system can enforce most of the constraints required by ownership-aware TM statically, and can enforce the remaining constraints dynamically. Finally, we prove that if transactions in the process of aborting obey restrictions on their memory footprint, then ownership-aware TM is free from semantic deadlock.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129551861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22

Session details: Programming model extensions 会话细节:编程模型扩展

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/3255509

Lauren M. Smith

引用次数: 0

An adaptive memory conscious approach for mining frequent trees: implications for multi-core architectures 挖掘频繁树的自适应内存意识方法:对多核架构的影响

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345247

S. Tatikonda, S. Parthasarathy

引用次数: 3

ZOID: I/O-forwarding infrastructure for petascale architectures ZOID:千兆级架构的I/ o转发基础设施

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345230

K. Iskra, J. Romein, Kazutomo Yoshii, P. Beckman

{"title":"ZOID: I/O-forwarding infrastructure for petascale architectures","authors":"K. Iskra, J. Romein, Kazutomo Yoshii, P. Beckman","doi":"10.1145/1345206.1345230","DOIUrl":"https://doi.org/10.1145/1345206.1345230","url":null,"abstract":"The ZeptoOS project is developing an open-source alternative to the proprietary software stacks available on contemporary massively parallel architectures. The aim is to enable computer science research on these architectures, enhance community collaboration, and foster innovation. In this paper, we introduce a component of ZeptoOS called ZOID---an I/O-forwarding infrastructure for architectures such as IBM Blue Gene that decouple file and socket I/O from the compute nodes, shipping those functions to dedicated I/O nodes. Through the use of optimized network protocols and data paths, as well as a multithreaded daemon running on I/O nodes, ZOID provides greater performance than does the stock infrastructure. We present a set of benchmark results that highlight the improvements. Crucially, the flexibility of our infrastructure is a vast improvement over the stock infrastructure, allowing users to forward data using custom-designed application interfaces, through an easy-to-use plug-in mechanism. This capability is used for real-time telescope data transfers, extensively discussed in the paper. Plug-in--specific threads implement prefetching of data obtained over sockets from an input cluster and merge results from individual compute nodes before sending them out, significantly reducing required network bandwidth. This approach allows a ZOID version of the application to handle a larger number of subbands per I/O node, or even to bypass the input cluster altogether, plugging the input from remote receiver stations directly into the I/O nodes. Using the resources more efficiently can result in considerable savings.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"PC-26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126677236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 107

Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories 具有显式管理内存的多级并行体系结构的自动数据移动和计算映射

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345210

M. Baskaran, Uday Bondhugula, S. Krishnamoorthy, J. Ramanujam, A. Rountev, P. Sadayappan

{"title":"Automatic data movement and computation mapping for multi-level parallel architectures with explicitly managed memories","authors":"M. Baskaran, Uday Bondhugula, S. Krishnamoorthy, J. Ramanujam, A. Rountev, P. Sadayappan","doi":"10.1145/1345206.1345210","DOIUrl":"https://doi.org/10.1145/1345206.1345210","url":null,"abstract":"Several parallel architectures such as GPUs and the Cell processor have fast explicitly managed on-chip memories, in addition to slow off-chip memory. They also have very high computational power with multiple levels of parallelism. A significant challenge in programming these architectures is to effectively exploit the parallelism available in the architecture and manage the fast memories to maximize performance. In this paper we develop an approach to effective automatic data management for on-chip memories, including creation of buffers in on-chip (local) memories for holding portions of data accessed in a computational block, automatic determination of array access functions of local buffer references, and generation of code that moves data between slow off-chip memory and fast local memories. We also address the problem of mapping computation in regular programs to multi-level parallel architectures using a multi-level tiling approach, and study the impact of on-chip memory availability on the selection of tile sizes at various levels. Experimental results on a GPU demonstrate the effectiveness of the proposed approach.","PeriodicalId":290559,"journal":{"name":"Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123025284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 129

Experience on optimizing irregular computation for memory hierarchy in manycore architecture 多核结构下内存层次结构不规则计算优化经验

Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming Pub Date : 2008-02-20 DOI: 10.1145/1345206.1345255

Guangming Tan, Dongrui Fan, Junchao Zhang, A. Russo, G. Gao

引用次数: 16